319 lines
12 KiB
C
319 lines
12 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Marek Vasut <marex@denx.de>
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/arch/sdram.h>
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/* Board-specific header. */
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#include <qts/sdram_config.h>
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static const struct socfpga_sdram_config sdram_config = {
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.ctrl_cfg =
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
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SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
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SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
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SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
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SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
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SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
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SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
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SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
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SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
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SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
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.dram_timing1 =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
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SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
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SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
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SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
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SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
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SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
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SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
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.dram_timing2 =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
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SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
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SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
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SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
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SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
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SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
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.dram_timing3 =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
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SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
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SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
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SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
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SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
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SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
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.dram_timing4 =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
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SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
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SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
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.lowpwr_timing =
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(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
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SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
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SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
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.dram_odt =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
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SDR_CTRLGRP_DRAMODT_READ_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
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SDR_CTRLGRP_DRAMODT_WRITE_LSB),
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.extratime1 =
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(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
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SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
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SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
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SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
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.dram_addrw =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
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SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
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SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
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SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) |
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((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
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SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
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.dram_if_width =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
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SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
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.dram_dev_width =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
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SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
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.dram_intr =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
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SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
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.lowpwr_eq =
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(CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
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SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
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.static_cfg =
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(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
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SDR_CTRLGRP_STATICCFG_MEMBL_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
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SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
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.ctrl_width =
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(CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
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SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
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.cport_width =
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(CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
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SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
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.cport_wmap =
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(CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
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SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
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.cport_rmap =
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(CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
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SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
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.rfifo_cmap =
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(CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
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SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
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.wfifo_cmap =
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(CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
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SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
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.cport_rdwr =
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(CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
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SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
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.port_cfg =
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(CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
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SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
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.fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
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.fifo_cfg =
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(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
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SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
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SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
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.mp_priority =
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(CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
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SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
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.mp_weight0 =
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(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
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SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
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.mp_weight1 =
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(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
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SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
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SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
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.mp_weight2 =
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(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
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SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
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.mp_weight3 =
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(CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
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SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
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.mp_pacing0 =
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(CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
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SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
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.mp_pacing1 =
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(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
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SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
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SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
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.mp_pacing2 =
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(CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
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SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
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.mp_pacing3 =
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(CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
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SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
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.mp_threshold0 =
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(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
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SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
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.mp_threshold1 =
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(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
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SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
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.mp_threshold2 =
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(CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
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SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
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.phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
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};
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static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
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.activate_0_and_1 = RW_MGR_ACTIVATE_0_AND_1,
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.activate_0_and_1_wait1 = RW_MGR_ACTIVATE_0_AND_1_WAIT1,
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.activate_0_and_1_wait2 = RW_MGR_ACTIVATE_0_AND_1_WAIT2,
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.activate_1 = RW_MGR_ACTIVATE_1,
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.clear_dqs_enable = RW_MGR_CLEAR_DQS_ENABLE,
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.guaranteed_read = RW_MGR_GUARANTEED_READ,
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.guaranteed_read_cont = RW_MGR_GUARANTEED_READ_CONT,
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.guaranteed_write = RW_MGR_GUARANTEED_WRITE,
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.guaranteed_write_wait0 = RW_MGR_GUARANTEED_WRITE_WAIT0,
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.guaranteed_write_wait1 = RW_MGR_GUARANTEED_WRITE_WAIT1,
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.guaranteed_write_wait2 = RW_MGR_GUARANTEED_WRITE_WAIT2,
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.guaranteed_write_wait3 = RW_MGR_GUARANTEED_WRITE_WAIT3,
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.idle = RW_MGR_IDLE,
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.idle_loop1 = RW_MGR_IDLE_LOOP1,
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.idle_loop2 = RW_MGR_IDLE_LOOP2,
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.init_reset_0_cke_0 = RW_MGR_INIT_RESET_0_CKE_0,
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.init_reset_1_cke_0 = RW_MGR_INIT_RESET_1_CKE_0,
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.lfsr_wr_rd_bank_0 = RW_MGR_LFSR_WR_RD_BANK_0,
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.lfsr_wr_rd_bank_0_data = RW_MGR_LFSR_WR_RD_BANK_0_DATA,
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.lfsr_wr_rd_bank_0_dqs = RW_MGR_LFSR_WR_RD_BANK_0_DQS,
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.lfsr_wr_rd_bank_0_nop = RW_MGR_LFSR_WR_RD_BANK_0_NOP,
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.lfsr_wr_rd_bank_0_wait = RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
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.lfsr_wr_rd_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_BANK_0_WL_1,
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.lfsr_wr_rd_dm_bank_0 = RW_MGR_LFSR_WR_RD_DM_BANK_0,
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.lfsr_wr_rd_dm_bank_0_data = RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
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.lfsr_wr_rd_dm_bank_0_dqs = RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
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.lfsr_wr_rd_dm_bank_0_nop = RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
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.lfsr_wr_rd_dm_bank_0_wait = RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
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.lfsr_wr_rd_dm_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1,
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.mrs0_dll_reset = RW_MGR_MRS0_DLL_RESET,
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.mrs0_dll_reset_mirr = RW_MGR_MRS0_DLL_RESET_MIRR,
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.mrs0_user = RW_MGR_MRS0_USER,
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.mrs0_user_mirr = RW_MGR_MRS0_USER_MIRR,
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.mrs1 = RW_MGR_MRS1,
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.mrs1_mirr = RW_MGR_MRS1_MIRR,
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.mrs2 = RW_MGR_MRS2,
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.mrs2_mirr = RW_MGR_MRS2_MIRR,
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.mrs3 = RW_MGR_MRS3,
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.mrs3_mirr = RW_MGR_MRS3_MIRR,
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.precharge_all = RW_MGR_PRECHARGE_ALL,
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.read_b2b = RW_MGR_READ_B2B,
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.read_b2b_wait1 = RW_MGR_READ_B2B_WAIT1,
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.read_b2b_wait2 = RW_MGR_READ_B2B_WAIT2,
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.refresh_all = RW_MGR_REFRESH_ALL,
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.rreturn = RW_MGR_RETURN,
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.sgle_read = RW_MGR_SGLE_READ,
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.zqcl = RW_MGR_ZQCL,
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.true_mem_data_mask_width = RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
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.mem_address_mirroring = RW_MGR_MEM_ADDRESS_MIRRORING,
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.mem_data_mask_width = RW_MGR_MEM_DATA_MASK_WIDTH,
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.mem_data_width = RW_MGR_MEM_DATA_WIDTH,
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.mem_dq_per_read_dqs = RW_MGR_MEM_DQ_PER_READ_DQS,
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.mem_dq_per_write_dqs = RW_MGR_MEM_DQ_PER_WRITE_DQS,
|
||
|
|
.mem_if_read_dqs_width = RW_MGR_MEM_IF_READ_DQS_WIDTH,
|
||
|
|
.mem_if_write_dqs_width = RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
|
||
|
|
.mem_number_of_cs_per_dimm = RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
|
||
|
|
.mem_number_of_ranks = RW_MGR_MEM_NUMBER_OF_RANKS,
|
||
|
|
.mem_virtual_groups_per_read_dqs =
|
||
|
|
RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
|
||
|
|
.mem_virtual_groups_per_write_dqs =
|
||
|
|
RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct socfpga_sdram_io_config io_config = {
|
||
|
|
.delay_per_dchain_tap = IO_DELAY_PER_DCHAIN_TAP,
|
||
|
|
.delay_per_dqs_en_dchain_tap = IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
|
||
|
|
.delay_per_opa_tap = IO_DELAY_PER_OPA_TAP,
|
||
|
|
.dll_chain_length = IO_DLL_CHAIN_LENGTH,
|
||
|
|
.dqdqs_out_phase_max = IO_DQDQS_OUT_PHASE_MAX,
|
||
|
|
.dqs_en_delay_max = IO_DQS_EN_DELAY_MAX,
|
||
|
|
.dqs_en_delay_offset = IO_DQS_EN_DELAY_OFFSET,
|
||
|
|
.dqs_en_phase_max = IO_DQS_EN_PHASE_MAX,
|
||
|
|
.dqs_in_delay_max = IO_DQS_IN_DELAY_MAX,
|
||
|
|
.dqs_in_reserve = IO_DQS_IN_RESERVE,
|
||
|
|
.dqs_out_reserve = IO_DQS_OUT_RESERVE,
|
||
|
|
.io_in_delay_max = IO_IO_IN_DELAY_MAX,
|
||
|
|
.io_out1_delay_max = IO_IO_OUT1_DELAY_MAX,
|
||
|
|
.io_out2_delay_max = IO_IO_OUT2_DELAY_MAX,
|
||
|
|
.shift_dqs_en_when_shift_dqs = IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct socfpga_sdram_misc_config misc_config = {
|
||
|
|
.afi_rate_ratio = AFI_RATE_RATIO,
|
||
|
|
.calib_lfifo_offset = CALIB_LFIFO_OFFSET,
|
||
|
|
.calib_vfifo_offset = CALIB_VFIFO_OFFSET,
|
||
|
|
.enable_super_quick_calibration = ENABLE_SUPER_QUICK_CALIBRATION,
|
||
|
|
.max_latency_count_width = MAX_LATENCY_COUNT_WIDTH,
|
||
|
|
.read_valid_fifo_size = READ_VALID_FIFO_SIZE,
|
||
|
|
.reg_file_init_seq_signature = REG_FILE_INIT_SEQ_SIGNATURE,
|
||
|
|
.tinit_cntr0_val = TINIT_CNTR0_VAL,
|
||
|
|
.tinit_cntr1_val = TINIT_CNTR1_VAL,
|
||
|
|
.tinit_cntr2_val = TINIT_CNTR2_VAL,
|
||
|
|
.treset_cntr0_val = TRESET_CNTR0_VAL,
|
||
|
|
.treset_cntr1_val = TRESET_CNTR1_VAL,
|
||
|
|
.treset_cntr2_val = TRESET_CNTR2_VAL,
|
||
|
|
};
|
||
|
|
|
||
|
|
const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
|
||
|
|
{
|
||
|
|
return &sdram_config;
|
||
|
|
}
|
||
|
|
|
||
|
|
void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem)
|
||
|
|
{
|
||
|
|
*init = ac_rom_init;
|
||
|
|
*nelem = ARRAY_SIZE(ac_rom_init);
|
||
|
|
}
|
||
|
|
|
||
|
|
void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem)
|
||
|
|
{
|
||
|
|
*init = inst_rom_init;
|
||
|
|
*nelem = ARRAY_SIZE(inst_rom_init);
|
||
|
|
}
|
||
|
|
|
||
|
|
const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void)
|
||
|
|
{
|
||
|
|
return &rw_mgr_config;
|
||
|
|
}
|
||
|
|
|
||
|
|
const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void)
|
||
|
|
{
|
||
|
|
return &io_config;
|
||
|
|
}
|
||
|
|
|
||
|
|
const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void)
|
||
|
|
{
|
||
|
|
return &misc_config;
|
||
|
|
}
|