89 lines
3.1 KiB
C
89 lines
3.1 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _CTRL_PEX_H
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#define _CTRL_PEX_H
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#include "high_speed_env_spec.h"
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/* Sample at Reset */
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#define MPP_SAMPLE_AT_RESET(id) (0xe4200 + (id * 4))
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/* PCI Express Control and Status Registers */
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#define MAX_PEX_BUSSES 256
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#define MISC_REGS_OFFSET 0x18200
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#define MV_MISC_REGS_BASE MISC_REGS_OFFSET
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#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4)
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#define PEX_IF_REGS_OFFSET(if) ((if) > 0 ? \
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(0x40000 + ((if) - 1) * 0x4000) : \
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0x80000)
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#define PEX_IF_REGS_BASE(if) (PEX_IF_REGS_OFFSET(if))
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#define PEX_CAPABILITIES_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x60)
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#define PEX_LINK_CTRL_STATUS2_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x90)
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#define PEX_CTRL_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a00)
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#define PEX_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a04)
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#define PEX_DBG_STATUS_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x1a64)
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#define PEX_LINK_CAPABILITY_REG 0x6c
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#define PEX_LINK_CTRL_STAT_REG 0x70
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#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */
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#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS)
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#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */
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#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS)
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/* PEX_CAPABILITIES_REG fields */
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#define PCIE0_ENABLE_OFFS 0
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#define PCIE0_ENABLE_MASK (0x1 << PCIE0_ENABLE_OFFS)
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#define PCIE1_ENABLE_OFFS 1
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#define PCIE1_ENABLE_MASK (0x1 << PCIE1_ENABLE_OFFS)
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#define PCIE2_ENABLE_OFFS 2
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#define PCIE2_ENABLE_MASK (0x1 << PCIE2_ENABLE_OFFS)
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#define PCIE3_ENABLE_OFFS 3
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#define PCIE4_ENABLE_MASK (0x1 << PCIE3_ENABLE_OFFS)
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/* Controller revision info */
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#define PEX_DEVICE_AND_VENDOR_ID 0x000
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#define PEX_CFG_DIRECT_ACCESS(if, reg) (PEX_IF_REGS_BASE(if) + (reg))
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/* PCI Express Configuration Address Register */
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#define PXCAR_REG_NUM_OFFS 2
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#define PXCAR_REG_NUM_MAX 0x3f
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#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << \
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PXCAR_REG_NUM_OFFS)
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#define PXCAR_FUNC_NUM_OFFS 8
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#define PXCAR_FUNC_NUM_MAX 0x7
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#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << \
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PXCAR_FUNC_NUM_OFFS)
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#define PXCAR_DEVICE_NUM_OFFS 11
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#define PXCAR_DEVICE_NUM_MAX 0x1f
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#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << \
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PXCAR_DEVICE_NUM_OFFS)
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#define PXCAR_BUS_NUM_OFFS 16
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#define PXCAR_BUS_NUM_MAX 0xff
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#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << \
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PXCAR_BUS_NUM_OFFS)
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#define PXCAR_EXT_REG_NUM_OFFS 24
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#define PXCAR_EXT_REG_NUM_MAX 0xf
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#define PEX_CFG_ADDR_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x18f8)
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#define PEX_CFG_DATA_REG(if) ((PEX_IF_REGS_BASE(if)) + 0x18fc)
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#define PXCAR_REAL_EXT_REG_NUM_OFFS 8
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#define PXCAR_REAL_EXT_REG_NUM_MASK (0xf << PXCAR_REAL_EXT_REG_NUM_OFFS)
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#define PXCAR_CONFIG_EN BIT(31)
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#define PEX_STATUS_AND_COMMAND 0x004
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#define PXSAC_MABORT BIT(29) /* Recieved Master Abort */
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int hws_pex_config(const struct serdes_map *serdes_map, u8 count);
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int pex_local_bus_num_set(u32 pex_if, u32 bus_num);
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int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
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u32 pex_config_read(u32 pex_if, u32 bus, u32 dev, u32 func, u32 reg_off);
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void board_pex_config(void);
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#endif
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