112 lines
3.0 KiB
C
112 lines
3.0 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* K2L: SoC definitions
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*/
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#ifndef __ASM_ARCH_HARDWARE_K2L_H
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#define __ASM_ARCH_HARDWARE_K2L_H
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#define KS2_ARM_PLL_EN BIT(13)
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/* PA SS Registers */
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#define KS2_PASS_BASE 0x26000000
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/* Power and Sleep Controller (PSC) Domains */
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#define KS2_LPSC_MOD 0
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#define KS2_LPSC_DFE_IQN_SYS 1
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#define KS2_LPSC_USB 2
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#define KS2_LPSC_EMIF25_SPI 3
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#define KS2_LPSC_TSIP 4
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#define KS2_LPSC_DEBUGSS_TRC 5
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#define KS2_LPSC_TETB_TRC 6
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#define KS2_LPSC_PKTPROC 7
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#define KS2_LPSC_PA KS2_LPSC_PKTPROC
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#define KS2_LPSC_SGMII 8
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#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
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#define KS2_LPSC_CRYPTO 9
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#define KS2_LPSC_PCIE0 10
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#define KS2_LPSC_PCIE1 11
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#define KS2_LPSC_JESD_MISC 12
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#define KS2_LPSC_CHIP_SRSS 13
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#define KS2_LPSC_MSMC 14
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#define KS2_LPSC_GEM_1 16
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#define KS2_LPSC_GEM_2 17
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#define KS2_LPSC_GEM_3 18
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#define KS2_LPSC_EMIF4F_DDR3 23
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#define KS2_LPSC_TAC 25
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#define KS2_LPSC_RAC 26
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#define KS2_LPSC_DDUC4X_CFR2X_BB 27
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#define KS2_LPSC_FFTC_A 28
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#define KS2_LPSC_OSR 34
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#define KS2_LPSC_TCP3D_0 35
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#define KS2_LPSC_TCP3D_1 37
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#define KS2_LPSC_VCP2X4_A 39
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#define KS2_LPSC_VCP2X4_B 40
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#define KS2_LPSC_VCP2X4_C 41
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#define KS2_LPSC_VCP2X4_D 42
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#define KS2_LPSC_BCP 47
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#define KS2_LPSC_DPD4X 48
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#define KS2_LPSC_FFTC_B 49
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#define KS2_LPSC_IQN_AIL 50
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/* Chip Interrupt Controller */
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#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
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#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
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/* OSR */
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#define KS2_OSR_DATA_BASE 0x70000000 /* OSR data base */
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#define KS2_OSR_CFG_BASE 0x02348c00 /* OSR config base */
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#define KS2_OSR_ECC_VEC 0x08 /* ECC Vector reg */
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#define KS2_OSR_ECC_CTRL 0x14 /* ECC control reg */
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/* OSR ECC Vector register */
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#define KS2_OSR_ECC_VEC_TRIG_RD BIT(15) /* trigger a read op */
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#define KS2_OSR_ECC_VEC_RD_DONE BIT(24) /* read complete */
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#define KS2_OSR_ECC_VEC_RAM_ID_SH 0 /* RAM ID shift */
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#define KS2_OSR_ECC_VEC_RD_ADDR_SH 16 /* read address shift */
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/* OSR ECC control register */
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#define KS2_OSR_ECC_CTRL_EN BIT(0) /* ECC enable bit */
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#define KS2_OSR_ECC_CTRL_CHK BIT(1) /* ECC check bit */
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#define KS2_OSR_ECC_CTRL_RMW BIT(2) /* ECC check bit */
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/* Number of OSR RAM banks */
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#define KS2_OSR_NUM_RAM_BANKS 4
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/* OSR memory size */
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#define KS2_OSR_SIZE 0x100000
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/* SGMII SerDes */
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#define KS2_SGMII_SERDES2_BASE 0x02320000
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#define KS2_LANES_PER_SGMII_SERDES 2
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/* Number of DSP cores */
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#define KS2_NUM_DSPS 4
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/* NETCP pktdma */
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#define KS2_NETCP_PDMA_CTRL_BASE 0x26186000
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#define KS2_NETCP_PDMA_TX_BASE 0x26187000
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#define KS2_NETCP_PDMA_TX_CH_NUM 21
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#define KS2_NETCP_PDMA_RX_BASE 0x26188000
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#define KS2_NETCP_PDMA_RX_CH_NUM 91
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#define KS2_NETCP_PDMA_SCHED_BASE 0x26186100
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#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x26189000
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#define KS2_NETCP_PDMA_RX_FLOW_NUM 96
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#define KS2_NETCP_PDMA_TX_SND_QUEUE 896
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/* NETCP */
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#define KS2_NETCP_BASE 0x26000000
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#ifndef __ASSEMBLY__
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static inline int ddr3_get_size(void)
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{
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return 2;
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}
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#endif
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#endif /* __ASM_ARCH_HARDWARE_K2L_H */
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