205 lines
7.3 KiB
C
205 lines
7.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* DDR controller configuration for the i.MX7 architecture
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*
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* (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
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*
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* Author: Uri Mashiach <uri.mashiach@compulab.co.il>
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*/
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#include <linux/types.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx7-ddr.h>
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#include <common.h>
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/*
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* Routine: mx7_dram_cfg
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* Description: DDR controller configuration
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*
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* @ddrc_regs_val: DDRC registers value
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* @ddrc_mp_val: DDRC_MP registers value
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* @ddr_phy_regs_val: DDR_PHY registers value
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* @calib_param: calibration parameters
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*
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*/
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void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
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struct ddr_phy *ddr_phy_regs_val,
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struct mx7_calibration *calib_param)
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{
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struct src *const src_regs = (struct src *)SRC_BASE_ADDR;
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struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;
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struct ddrc_mp *const ddrc_mp_reg = (struct ddrc_mp *)DDRC_MP_BASE_ADDR;
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struct ddr_phy *const ddr_phy_regs =
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(struct ddr_phy *)DDRPHY_IPS_BASE_ADDR;
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struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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int i;
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/* Assert DDR Controller preset and DDR PHY reset */
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writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK, &src_regs->ddrc_rcr);
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/* DDR controller configuration */
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writel(ddrc_regs_val->mstr, &ddrc_regs->mstr);
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writel(ddrc_regs_val->rfshtmg, &ddrc_regs->rfshtmg);
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writel(ddrc_mp_val->pctrl_0, &ddrc_mp_reg->pctrl_0);
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writel(ddrc_regs_val->init1, &ddrc_regs->init1);
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writel(ddrc_regs_val->init0, &ddrc_regs->init0);
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writel(ddrc_regs_val->init3, &ddrc_regs->init3);
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writel(ddrc_regs_val->init4, &ddrc_regs->init4);
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writel(ddrc_regs_val->init5, &ddrc_regs->init5);
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writel(ddrc_regs_val->rankctl, &ddrc_regs->rankctl);
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writel(ddrc_regs_val->dramtmg0, &ddrc_regs->dramtmg0);
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writel(ddrc_regs_val->dramtmg1, &ddrc_regs->dramtmg1);
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writel(ddrc_regs_val->dramtmg2, &ddrc_regs->dramtmg2);
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writel(ddrc_regs_val->dramtmg3, &ddrc_regs->dramtmg3);
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writel(ddrc_regs_val->dramtmg4, &ddrc_regs->dramtmg4);
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writel(ddrc_regs_val->dramtmg5, &ddrc_regs->dramtmg5);
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writel(ddrc_regs_val->dramtmg8, &ddrc_regs->dramtmg8);
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writel(ddrc_regs_val->zqctl0, &ddrc_regs->zqctl0);
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writel(ddrc_regs_val->dfitmg0, &ddrc_regs->dfitmg0);
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writel(ddrc_regs_val->dfitmg1, &ddrc_regs->dfitmg1);
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writel(ddrc_regs_val->dfiupd0, &ddrc_regs->dfiupd0);
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writel(ddrc_regs_val->dfiupd1, &ddrc_regs->dfiupd1);
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writel(ddrc_regs_val->dfiupd2, &ddrc_regs->dfiupd2);
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writel(ddrc_regs_val->addrmap0, &ddrc_regs->addrmap0);
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writel(ddrc_regs_val->addrmap1, &ddrc_regs->addrmap1);
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writel(ddrc_regs_val->addrmap4, &ddrc_regs->addrmap4);
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writel(ddrc_regs_val->addrmap5, &ddrc_regs->addrmap5);
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writel(ddrc_regs_val->addrmap6, &ddrc_regs->addrmap6);
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writel(ddrc_regs_val->odtcfg, &ddrc_regs->odtcfg);
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writel(ddrc_regs_val->odtmap, &ddrc_regs->odtmap);
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/* De-assert DDR Controller preset and DDR PHY reset */
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clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_CORE_RST_MASK);
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/* PHY configuration */
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writel(ddr_phy_regs_val->phy_con0, &ddr_phy_regs->phy_con0);
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writel(ddr_phy_regs_val->phy_con1, &ddr_phy_regs->phy_con1);
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writel(ddr_phy_regs_val->phy_con4, &ddr_phy_regs->phy_con4);
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writel(ddr_phy_regs_val->mdll_con0, &ddr_phy_regs->mdll_con0);
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writel(ddr_phy_regs_val->drvds_con0, &ddr_phy_regs->drvds_con0);
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writel(ddr_phy_regs_val->offset_wr_con0, &ddr_phy_regs->offset_wr_con0);
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writel(ddr_phy_regs_val->offset_rd_con0, &ddr_phy_regs->offset_rd_con0);
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writel(ddr_phy_regs_val->cmd_sdll_con0 |
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DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,
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&ddr_phy_regs->cmd_sdll_con0);
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writel(ddr_phy_regs_val->cmd_sdll_con0 &
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~DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,
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&ddr_phy_regs->cmd_sdll_con0);
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writel(ddr_phy_regs_val->offset_lp_con0, &ddr_phy_regs->offset_lp_con0);
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/* calibration */
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for (i = 0; i < calib_param->num_val; i++)
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writel(calib_param->values[i], &ddr_phy_regs->zq_con0);
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/* Wake_up DDR PHY */
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HW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_N_N);
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writel(IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(0xf) |
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IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK,
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&iomuxc_gpr_regs->gpr[8]);
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HW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_R_W);
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}
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/*
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* Routine: imx_ddr_size
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* Description: extract the current DRAM size from the DDRC registers
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*
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* @return: DRAM size
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*/
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unsigned int imx_ddr_size(void)
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{
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struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;
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u32 reg_val, field_val;
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int bits = 0;/* Number of address bits */
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/* Count data bus width bits */
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reg_val = readl(&ddrc_regs->mstr);
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field_val = (reg_val & MSTR_DATA_BUS_WIDTH_MASK) >> MSTR_DATA_BUS_WIDTH_SHIFT;
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bits += 2 - field_val;
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/* Count rank address bits */
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field_val = (reg_val & MSTR_DATA_ACTIVE_RANKS_MASK) >> MSTR_DATA_ACTIVE_RANKS_SHIFT;
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if (field_val > 1)
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bits += field_val - 1;
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/* Count column address bits */
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bits += 2;/* Column address 0 and 1 are fixed mapped */
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reg_val = readl(&ddrc_regs->addrmap2);
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field_val = (reg_val & ADDRMAP2_COL_B2_MASK) >> ADDRMAP2_COL_B2_SHIFT;
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if (field_val <= 7)
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bits++;
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field_val = (reg_val & ADDRMAP2_COL_B3_MASK) >> ADDRMAP2_COL_B3_SHIFT;
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if (field_val <= 7)
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bits++;
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field_val = (reg_val & ADDRMAP2_COL_B4_MASK) >> ADDRMAP2_COL_B4_SHIFT;
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if (field_val <= 7)
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bits++;
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field_val = (reg_val & ADDRMAP2_COL_B5_MASK) >> ADDRMAP2_COL_B5_SHIFT;
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if (field_val <= 7)
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bits++;
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reg_val = readl(&ddrc_regs->addrmap3);
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field_val = (reg_val & ADDRMAP3_COL_B6_MASK) >> ADDRMAP3_COL_B6_SHIFT;
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if (field_val <= 7)
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bits++;
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field_val = (reg_val & ADDRMAP3_COL_B7_MASK) >> ADDRMAP3_COL_B7_SHIFT;
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if (field_val <= 7)
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bits++;
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field_val = (reg_val & ADDRMAP3_COL_B8_MASK) >> ADDRMAP3_COL_B8_SHIFT;
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if (field_val <= 7)
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bits++;
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field_val = (reg_val & ADDRMAP3_COL_B9_MASK) >> ADDRMAP3_COL_B9_SHIFT;
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if (field_val <= 7)
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bits++;
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reg_val = readl(&ddrc_regs->addrmap4);
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field_val = (reg_val & ADDRMAP4_COL_B10_MASK) >> ADDRMAP4_COL_B10_SHIFT;
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if (field_val <= 7)
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bits++;
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field_val = (reg_val & ADDRMAP4_COL_B11_MASK) >> ADDRMAP4_COL_B11_SHIFT;
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if (field_val <= 7)
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bits++;
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/* Count row address bits */
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reg_val = readl(&ddrc_regs->addrmap5);
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field_val = (reg_val & ADDRMAP5_ROW_B0_MASK) >> ADDRMAP5_ROW_B0_SHIFT;
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if (field_val <= 11)
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bits++;
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field_val = (reg_val & ADDRMAP5_ROW_B1_MASK) >> ADDRMAP5_ROW_B1_SHIFT;
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if (field_val <= 11)
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bits++;
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field_val = (reg_val & ADDRMAP5_ROW_B2_10_MASK) >> ADDRMAP5_ROW_B2_10_SHIFT;
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if (field_val <= 11)
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bits += 9;
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field_val = (reg_val & ADDRMAP5_ROW_B11_MASK) >> ADDRMAP5_ROW_B11_SHIFT;
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if (field_val <= 11)
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bits++;
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reg_val = readl(&ddrc_regs->addrmap6);
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field_val = (reg_val & ADDRMAP6_ROW_B12_MASK) >> ADDRMAP6_ROW_B12_SHIFT;
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if (field_val <= 11)
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bits++;
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field_val = (reg_val & ADDRMAP6_ROW_B13_MASK) >> ADDRMAP6_ROW_B13_SHIFT;
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if (field_val <= 11)
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bits++;
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field_val = (reg_val & ADDRMAP6_ROW_B14_MASK) >> ADDRMAP6_ROW_B14_SHIFT;
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if (field_val <= 11)
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bits++;
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field_val = (reg_val & ADDRMAP6_ROW_B15_MASK) >> ADDRMAP6_ROW_B15_SHIFT;
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if (field_val <= 11)
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bits++;
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/* Count bank bits */
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reg_val = readl(&ddrc_regs->addrmap1);
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field_val = (reg_val & ADDRMAP1_BANK_B0_MASK) >> ADDRMAP1_BANK_B0_SHIFT;
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if (field_val <= 30)
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bits++;
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field_val = (reg_val & ADDRMAP1_BANK_B1_MASK) >> ADDRMAP1_BANK_B1_SHIFT;
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if (field_val <= 30)
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bits++;
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field_val = (reg_val & ADDRMAP1_BANK_B2_MASK) >> ADDRMAP1_BANK_B2_SHIFT;
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if (field_val <= 29)
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bits++;
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/* cap to max 2 GB */
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if (bits > 31)
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bits = 31;
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return 1 << bits;
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}
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