68 lines
1.7 KiB
C
68 lines
1.7 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com>
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*/
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#ifndef _SUNXI_DMA_SUN4I_H
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#define _SUNXI_DMA_SUN4I_H
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struct sunxi_dma_cfg
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{
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u32 ctl; /* 0x00 Control */
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u32 src_addr; /* 0x04 Source address */
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u32 dst_addr; /* 0x08 Destination address */
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u32 bc; /* 0x0C Byte counter */
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u32 res0[2];
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u32 ddma_para; /* 0x18 extra parameter (dedicated DMA only) */
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u32 res1;
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};
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struct sunxi_dma
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{
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u32 irq_en; /* 0x000 IRQ enable */
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u32 irq_pend; /* 0x004 IRQ pending */
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u32 auto_gate; /* 0x008 auto gating */
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u32 res0[61];
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struct sunxi_dma_cfg ndma[8]; /* 0x100 Normal DMA */
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u32 res1[64];
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struct sunxi_dma_cfg ddma[8]; /* 0x300 Dedicated DMA */
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};
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enum ddma_drq_type {
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DDMA_DST_DRQ_SRAM = 0,
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DDMA_SRC_DRQ_SRAM = 0,
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DDMA_DST_DRQ_SDRAM = 1,
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DDMA_SRC_DRQ_SDRAM = 1,
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DDMA_DST_DRQ_PATA = 2,
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DDMA_SRC_DRQ_PATA = 2,
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DDMA_DST_DRQ_NAND = 3,
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DDMA_SRC_DRQ_NAND = 3,
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DDMA_DST_DRQ_USB0 = 4,
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DDMA_SRC_DRQ_USB0 = 4,
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DDMA_DST_DRQ_ETHERNET_MAC_TX = 6,
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DDMA_SRC_DRQ_ETHERNET_MAC_RX = 7,
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DDMA_DST_DRQ_SPI1_TX = 8,
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DDMA_SRC_DRQ_SPI1_RX = 9,
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DDMA_DST_DRQ_SECURITY_SYS_TX = 10,
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DDMA_SRC_DRQ_SECURITY_SYS_RX = 11,
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DDMA_DST_DRQ_TCON0 = 14,
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DDMA_DST_DRQ_TCON1 = 15,
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DDMA_DST_DRQ_MSC = 23,
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DDMA_SRC_DRQ_MSC = 23,
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DDMA_DST_DRQ_SPI0_TX = 26,
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DDMA_SRC_DRQ_SPI0_RX = 27,
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DDMA_DST_DRQ_SPI2_TX = 28,
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DDMA_SRC_DRQ_SPI2_RX = 29,
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DDMA_DST_DRQ_SPI3_TX = 30,
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DDMA_SRC_DRQ_SPI3_RX = 31,
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};
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#define SUNXI_DMA_CTL_SRC_DRQ(a) ((a) & 0x1f)
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#define SUNXI_DMA_CTL_MODE_IO (1 << 5)
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#define SUNXI_DMA_CTL_SRC_DATA_WIDTH_32 (2 << 9)
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#define SUNXI_DMA_CTL_DST_DRQ(a) (((a) & 0x1f) << 16)
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#define SUNXI_DMA_CTL_DST_DATA_WIDTH_32 (2 << 25)
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#define SUNXI_DMA_CTL_TRIGGER (1 << 31)
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#endif /* _SUNXI_DMA_SUN4I_H */
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