83 lines
2.2 KiB
C
83 lines
2.2 KiB
C
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/*
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* linux/include/asm-arm/arch-pxa/hardware.h
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Note: This file was taken from linux-2.4.19-rmk4-pxa1
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*
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* - 2003/01/20 implementation specifics activated
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* Robert Schwebel <r.schwebel@pengutronix.de>
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include <asm/mach-types.h>
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/*
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* Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected.
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* PXA300/310/320 all have distinct register mappings in some cases, that's why
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* the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common
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* drivers and compatibility glue with old source then.
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*/
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#ifndef CONFIG_CPU_MONAHANS
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#if defined(CONFIG_CPU_PXA300) || \
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defined(CONFIG_CPU_PXA310) || \
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defined(CONFIG_CPU_PXA320)
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#define CONFIG_CPU_MONAHANS
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#endif
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#endif
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/*
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* These are statically mapped PCMCIA IO space for designs using it as a
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* generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc.
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* The actual PCMCIA code is mapping required IO region at run time.
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*/
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#define PCMCIA_IO_0_BASE 0xf6000000
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#define PCMCIA_IO_1_BASE 0xf7000000
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/*
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* We requires absolute addresses.
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*/
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#define PCIO_BASE 0
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/*
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* Workarounds for at least 2 errata so far require this.
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* The mapping is set in mach-pxa/generic.c.
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*/
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#define UNCACHED_PHYS_0 0xff000000
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#define UNCACHED_ADDR UNCACHED_PHYS_0
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/*
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* Intel PXA internal I/O mappings:
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*
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* 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff
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* 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff
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* 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
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*/
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#include "pxa-regs.h"
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#ifndef __ASSEMBLY__
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/*
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* GPIO edge detection for IRQs:
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* IRQs are generated on Falling-Edge, Rising-Edge, or both.
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* This must be called *before* the corresponding IRQ is registered.
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* Use this instead of directly setting GRER/GFER.
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*/
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#define GPIO_FALLING_EDGE 1
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#define GPIO_RISING_EDGE 2
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#define GPIO_BOTH_EDGES 3
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#endif
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#endif /* _ASM_ARCH_HARDWARE_H */
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