116 lines
3.0 KiB
C
116 lines
3.0 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
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*
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* Author:
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* Peng Fan <Peng.Fan@freescale.com>
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*/
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#ifndef _ASM_ARCH_CLOCK_SLICE_H
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#define _ASM_ARCH_CLOCK_SLICE_H
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enum root_pre_div {
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CLK_ROOT_PRE_DIV1 = 0,
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CLK_ROOT_PRE_DIV2,
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CLK_ROOT_PRE_DIV3,
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CLK_ROOT_PRE_DIV4,
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CLK_ROOT_PRE_DIV5,
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CLK_ROOT_PRE_DIV6,
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CLK_ROOT_PRE_DIV7,
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CLK_ROOT_PRE_DIV8,
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};
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enum root_post_div {
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CLK_ROOT_POST_DIV1 = 0,
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CLK_ROOT_POST_DIV2,
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CLK_ROOT_POST_DIV3,
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CLK_ROOT_POST_DIV4,
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CLK_ROOT_POST_DIV5,
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CLK_ROOT_POST_DIV6,
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CLK_ROOT_POST_DIV7,
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CLK_ROOT_POST_DIV8,
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CLK_ROOT_POST_DIV9,
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CLK_ROOT_POST_DIV10,
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CLK_ROOT_POST_DIV11,
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CLK_ROOT_POST_DIV12,
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CLK_ROOT_POST_DIV13,
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CLK_ROOT_POST_DIV14,
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CLK_ROOT_POST_DIV15,
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CLK_ROOT_POST_DIV16,
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CLK_ROOT_POST_DIV17,
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CLK_ROOT_POST_DIV18,
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CLK_ROOT_POST_DIV19,
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CLK_ROOT_POST_DIV20,
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CLK_ROOT_POST_DIV21,
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CLK_ROOT_POST_DIV22,
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CLK_ROOT_POST_DIV23,
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CLK_ROOT_POST_DIV24,
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CLK_ROOT_POST_DIV25,
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CLK_ROOT_POST_DIV26,
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CLK_ROOT_POST_DIV27,
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CLK_ROOT_POST_DIV28,
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CLK_ROOT_POST_DIV29,
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CLK_ROOT_POST_DIV30,
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CLK_ROOT_POST_DIV31,
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CLK_ROOT_POST_DIV32,
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CLK_ROOT_POST_DIV33,
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CLK_ROOT_POST_DIV34,
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CLK_ROOT_POST_DIV35,
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CLK_ROOT_POST_DIV36,
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CLK_ROOT_POST_DIV37,
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CLK_ROOT_POST_DIV38,
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CLK_ROOT_POST_DIV39,
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CLK_ROOT_POST_DIV40,
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CLK_ROOT_POST_DIV41,
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CLK_ROOT_POST_DIV42,
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CLK_ROOT_POST_DIV43,
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CLK_ROOT_POST_DIV44,
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CLK_ROOT_POST_DIV45,
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CLK_ROOT_POST_DIV46,
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CLK_ROOT_POST_DIV47,
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CLK_ROOT_POST_DIV48,
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CLK_ROOT_POST_DIV49,
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CLK_ROOT_POST_DIV50,
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CLK_ROOT_POST_DIV51,
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CLK_ROOT_POST_DIV52,
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CLK_ROOT_POST_DIV53,
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CLK_ROOT_POST_DIV54,
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CLK_ROOT_POST_DIV55,
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CLK_ROOT_POST_DIV56,
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CLK_ROOT_POST_DIV57,
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CLK_ROOT_POST_DIV58,
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CLK_ROOT_POST_DIV59,
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CLK_ROOT_POST_DIV60,
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CLK_ROOT_POST_DIV61,
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CLK_ROOT_POST_DIV62,
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CLK_ROOT_POST_DIV63,
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CLK_ROOT_POST_DIV64,
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};
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enum root_auto_div {
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CLK_ROOT_AUTO_DIV1 = 0,
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CLK_ROOT_AUTO_DIV2,
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CLK_ROOT_AUTO_DIV4,
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CLK_ROOT_AUTO_DIV8,
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CLK_ROOT_AUTO_DIV16,
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};
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int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src);
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int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
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int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div);
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int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
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int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div);
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int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div);
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int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div,
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int auto_en);
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int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div,
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int *auto_en);
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int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
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int clock_set_target_val(enum clk_root_index clock_id, u32 val);
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int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
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enum root_post_div post_div, enum clk_root_src clock_src);
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int clock_root_enabled(enum clk_root_index clock_id);
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int clock_enable(enum clk_ccgr_index index, bool enable);
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#endif
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