525 lines
15 KiB
Plaintext
525 lines
15 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
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* Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
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*/
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&pinctrl {
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m4_adc1_in6_pins_a: m4-adc1-in6 {
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pins {
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pinmux = <STM32_PINMUX('F', 12, RSVD)>;
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};
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};
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m4_adc12_ain_pins_a: m4-adc12-ain-0 {
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pins {
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pinmux = <STM32_PINMUX('C', 3, RSVD)>, /* ADC1 in13 */
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<STM32_PINMUX('F', 12, RSVD)>, /* ADC1 in6 */
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<STM32_PINMUX('F', 13, RSVD)>, /* ADC2 in2 */
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<STM32_PINMUX('F', 14, RSVD)>; /* ADC2 in6 */
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};
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};
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m4_adc12_usb_pwr_pins_a: m4-adc12-usb-pwr-pins-0 {
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pins {
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pinmux = <STM32_PINMUX('A', 4, RSVD)>, /* ADC12 in18 */
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<STM32_PINMUX('A', 5, RSVD)>; /* ADC12 in19 */
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};
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};
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m4_cec_pins_a: m4-cec-0 {
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pins {
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pinmux = <STM32_PINMUX('A', 15, RSVD)>;
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};
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};
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m4_cec_pins_b: m4-cec-1 {
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pins {
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pinmux = <STM32_PINMUX('B', 6, RSVD)>;
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};
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};
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m4_dac_ch1_pins_a: m4-dac-ch1 {
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pins {
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pinmux = <STM32_PINMUX('A', 4, RSVD)>;
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};
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};
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m4_dac_ch2_pins_a: m4-dac-ch2 {
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pins {
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pinmux = <STM32_PINMUX('A', 5, RSVD)>;
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};
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};
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m4_dcmi_pins_a: m4-dcmi-0 {
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pins {
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pinmux = <STM32_PINMUX('H', 8, RSVD)>,/* DCMI_HSYNC */
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<STM32_PINMUX('B', 7, RSVD)>,/* DCMI_VSYNC */
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<STM32_PINMUX('A', 6, RSVD)>,/* DCMI_PIXCLK */
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<STM32_PINMUX('H', 9, RSVD)>,/* DCMI_D0 */
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<STM32_PINMUX('H', 10, RSVD)>,/* DCMI_D1 */
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<STM32_PINMUX('H', 11, RSVD)>,/* DCMI_D2 */
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<STM32_PINMUX('H', 12, RSVD)>,/* DCMI_D3 */
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<STM32_PINMUX('H', 14, RSVD)>,/* DCMI_D4 */
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<STM32_PINMUX('I', 4, RSVD)>,/* DCMI_D5 */
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<STM32_PINMUX('B', 8, RSVD)>,/* DCMI_D6 */
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<STM32_PINMUX('E', 6, RSVD)>,/* DCMI_D7 */
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<STM32_PINMUX('I', 1, RSVD)>,/* DCMI_D8 */
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<STM32_PINMUX('H', 7, RSVD)>,/* DCMI_D9 */
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<STM32_PINMUX('I', 3, RSVD)>,/* DCMI_D10 */
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<STM32_PINMUX('H', 15, RSVD)>;/* DCMI_D11 */
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};
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};
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m4_dfsdm_clkout_pins_a: m4-dfsdm-clkout-pins-0 {
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pins {
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pinmux = <STM32_PINMUX('B', 13, RSVD)>; /* DFSDM_CKOUT */
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};
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};
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m4_dfsdm_data1_pins_a: m4-dfsdm-data1-pins-0 {
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pins {
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pinmux = <STM32_PINMUX('C', 3, RSVD)>; /* DFSDM_DATA1 */
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};
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};
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m4_dfsdm_data3_pins_a: m4-dfsdm-data3-pins-0 {
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pins {
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pinmux = <STM32_PINMUX('F', 13, RSVD)>; /* DFSDM_DATA3 */
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};
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};
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m4_ethernet0_rgmii_pins_a: m4-rgmii-0 {
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pins {
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pinmux = <STM32_PINMUX('G', 5, RSVD)>, /* ETH_RGMII_CLK125 */
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<STM32_PINMUX('G', 4, RSVD)>, /* ETH_RGMII_GTX_CLK */
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<STM32_PINMUX('G', 13, RSVD)>, /* ETH_RGMII_TXD0 */
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<STM32_PINMUX('G', 14, RSVD)>, /* ETH_RGMII_TXD1 */
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<STM32_PINMUX('C', 2, RSVD)>, /* ETH_RGMII_TXD2 */
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<STM32_PINMUX('E', 2, RSVD)>, /* ETH_RGMII_TXD3 */
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<STM32_PINMUX('B', 11, RSVD)>, /* ETH_RGMII_TX_CTL */
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<STM32_PINMUX('C', 1, RSVD)>, /* ETH_MDC */
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<STM32_PINMUX('A', 2, RSVD)>, /* ETH_MDIO */
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<STM32_PINMUX('C', 4, RSVD)>, /* ETH_RGMII_RXD0 */
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<STM32_PINMUX('C', 5, RSVD)>, /* ETH_RGMII_RXD1 */
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<STM32_PINMUX('B', 0, RSVD)>, /* ETH_RGMII_RXD2 */
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<STM32_PINMUX('B', 1, RSVD)>, /* ETH_RGMII_RXD3 */
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<STM32_PINMUX('A', 1, RSVD)>, /* ETH_RGMII_RX_CLK */
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<STM32_PINMUX('A', 7, RSVD)>; /* ETH_RGMII_RX_CTL */
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};
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};
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m4_fmc_pins_a: m4-fmc-0 {
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pins {
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pinmux = <STM32_PINMUX('D', 4, RSVD)>, /* FMC_NOE */
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<STM32_PINMUX('D', 5, RSVD)>, /* FMC_NWE */
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<STM32_PINMUX('D', 11, RSVD)>, /* FMC_A16_FMC_CLE */
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<STM32_PINMUX('D', 12, RSVD)>, /* FMC_A17_FMC_ALE */
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<STM32_PINMUX('D', 14, RSVD)>, /* FMC_D0 */
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<STM32_PINMUX('D', 15, RSVD)>, /* FMC_D1 */
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<STM32_PINMUX('D', 0, RSVD)>, /* FMC_D2 */
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<STM32_PINMUX('D', 1, RSVD)>, /* FMC_D3 */
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<STM32_PINMUX('E', 7, RSVD)>, /* FMC_D4 */
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<STM32_PINMUX('E', 8, RSVD)>, /* FMC_D5 */
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<STM32_PINMUX('E', 9, RSVD)>, /* FMC_D6 */
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<STM32_PINMUX('E', 10, RSVD)>, /* FMC_D7 */
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<STM32_PINMUX('G', 9, RSVD)>, /* FMC_NE2_FMC_NCE */
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<STM32_PINMUX('D', 6, RSVD)>; /* FMC_NWAIT */
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};
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};
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m4_hdp0_pins_a: m4-hdp0-0 {
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pins {
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pinmux = <STM32_PINMUX('I', 12, RSVD)>; /* HDP0 */
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};
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};
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m4_hdp6_pins_a: m4-hdp6-0 {
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pins {
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pinmux = <STM32_PINMUX('K', 5, RSVD)>; /* HDP6 */
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};
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};
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m4_hdp7_pins_a: m4-hdp7-0 {
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pins {
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pinmux = <STM32_PINMUX('K', 6, RSVD)>; /* HDP7 */
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};
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};
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m4_i2c1_pins_a: m4-i2c1-0 {
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pins {
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pinmux = <STM32_PINMUX('D', 12, RSVD)>, /* I2C1_SCL */
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<STM32_PINMUX('F', 15, RSVD)>; /* I2C1_SDA */
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};
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};
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m4_i2c2_pins_a: m4-i2c2-0 {
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pins {
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pinmux = <STM32_PINMUX('H', 4, RSVD)>, /* I2C2_SCL */
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<STM32_PINMUX('H', 5, RSVD)>; /* I2C2_SDA */
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};
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};
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m4_i2c5_pins_a: m4-i2c5-0 {
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pins {
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pinmux = <STM32_PINMUX('A', 11, RSVD)>, /* I2C5_SCL */
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<STM32_PINMUX('A', 12, RSVD)>; /* I2C5_SDA */
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};
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};
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m4_i2s2_pins_a: m4-i2s2-0 {
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pins {
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pinmux = <STM32_PINMUX('I', 3, RSVD)>, /* I2S2_SDO */
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<STM32_PINMUX('B', 9, RSVD)>, /* I2S2_WS */
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<STM32_PINMUX('A', 9, RSVD)>; /* I2S2_CK */
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};
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};
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m4_ltdc_pins_a: m4-ltdc-a-0 {
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pins {
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pinmux = <STM32_PINMUX('G', 7, RSVD)>, /* LCD_CLK */
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<STM32_PINMUX('I', 10, RSVD)>, /* LCD_HSYNC */
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<STM32_PINMUX('I', 9, RSVD)>, /* LCD_VSYNC */
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<STM32_PINMUX('F', 10, RSVD)>, /* LCD_DE */
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<STM32_PINMUX('H', 2, RSVD)>, /* LCD_R0 */
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<STM32_PINMUX('H', 3, RSVD)>, /* LCD_R1 */
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<STM32_PINMUX('H', 8, RSVD)>, /* LCD_R2 */
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<STM32_PINMUX('H', 9, RSVD)>, /* LCD_R3 */
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<STM32_PINMUX('H', 10, RSVD)>, /* LCD_R4 */
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<STM32_PINMUX('C', 0, RSVD)>, /* LCD_R5 */
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<STM32_PINMUX('H', 12, RSVD)>, /* LCD_R6 */
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<STM32_PINMUX('E', 15, RSVD)>, /* LCD_R7 */
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<STM32_PINMUX('E', 5, RSVD)>, /* LCD_G0 */
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<STM32_PINMUX('E', 6, RSVD)>, /* LCD_G1 */
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<STM32_PINMUX('H', 13, RSVD)>, /* LCD_G2 */
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<STM32_PINMUX('H', 14, RSVD)>, /* LCD_G3 */
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<STM32_PINMUX('H', 15, RSVD)>, /* LCD_G4 */
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<STM32_PINMUX('I', 0, RSVD)>, /* LCD_G5 */
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<STM32_PINMUX('I', 1, RSVD)>, /* LCD_G6 */
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<STM32_PINMUX('I', 2, RSVD)>, /* LCD_G7 */
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<STM32_PINMUX('D', 9, RSVD)>, /* LCD_B0 */
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<STM32_PINMUX('G', 12, RSVD)>, /* LCD_B1 */
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<STM32_PINMUX('G', 10, RSVD)>, /* LCD_B2 */
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<STM32_PINMUX('D', 10, RSVD)>, /* LCD_B3 */
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<STM32_PINMUX('I', 4, RSVD)>, /* LCD_B4 */
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<STM32_PINMUX('A', 3, RSVD)>, /* LCD_B5 */
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<STM32_PINMUX('B', 8, RSVD)>, /* LCD_B6 */
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<STM32_PINMUX('D', 8, RSVD)>; /* LCD_B7 */
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};
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};
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m4_ltdc_pins_b: m4-ltdc-b-0 {
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pins {
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pinmux = <STM32_PINMUX('I', 14, RSVD)>, /* LCD_CLK */
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<STM32_PINMUX('I', 12, RSVD)>, /* LCD_HSYNC */
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<STM32_PINMUX('I', 13, RSVD)>, /* LCD_VSYNC */
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<STM32_PINMUX('K', 7, RSVD)>, /* LCD_DE */
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<STM32_PINMUX('I', 15, RSVD)>, /* LCD_R0 */
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<STM32_PINMUX('J', 0, RSVD)>, /* LCD_R1 */
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<STM32_PINMUX('J', 1, RSVD)>, /* LCD_R2 */
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<STM32_PINMUX('J', 2, RSVD)>, /* LCD_R3 */
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<STM32_PINMUX('J', 3, RSVD)>, /* LCD_R4 */
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<STM32_PINMUX('J', 4, RSVD)>, /* LCD_R5 */
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<STM32_PINMUX('J', 5, RSVD)>, /* LCD_R6 */
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<STM32_PINMUX('J', 6, RSVD)>, /* LCD_R7 */
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<STM32_PINMUX('J', 7, RSVD)>, /* LCD_G0 */
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<STM32_PINMUX('J', 8, RSVD)>, /* LCD_G1 */
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<STM32_PINMUX('J', 9, RSVD)>, /* LCD_G2 */
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<STM32_PINMUX('J', 10, RSVD)>, /* LCD_G3 */
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<STM32_PINMUX('J', 11, RSVD)>, /* LCD_G4 */
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<STM32_PINMUX('K', 0, RSVD)>, /* LCD_G5 */
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<STM32_PINMUX('K', 1, RSVD)>, /* LCD_G6 */
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<STM32_PINMUX('K', 2, RSVD)>, /* LCD_G7 */
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<STM32_PINMUX('J', 12, RSVD)>, /* LCD_B0 */
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<STM32_PINMUX('J', 13, RSVD)>, /* LCD_B1 */
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<STM32_PINMUX('J', 14, RSVD)>, /* LCD_B2 */
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<STM32_PINMUX('J', 15, RSVD)>, /* LCD_B3 */
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<STM32_PINMUX('K', 3, RSVD)>, /* LCD_B4 */
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<STM32_PINMUX('K', 4, RSVD)>, /* LCD_B5 */
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<STM32_PINMUX('K', 5, RSVD)>, /* LCD_B6 */
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<STM32_PINMUX('K', 6, RSVD)>; /* LCD_B7 */
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};
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};
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m4_m_can1_pins_a: m4-m-can1-0 {
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pins {
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pinmux = <STM32_PINMUX('H', 13, RSVD)>, /* CAN1_TX */
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<STM32_PINMUX('I', 9, RSVD)>; /* CAN1_RX */
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};
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};
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m4_pwm1_pins_a: m4-pwm1-0 {
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pins {
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pinmux = <STM32_PINMUX('E', 9, RSVD)>, /* TIM1_CH1 */
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<STM32_PINMUX('E', 11, RSVD)>, /* TIM1_CH2 */
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<STM32_PINMUX('E', 14, RSVD)>; /* TIM1_CH4 */
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};
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};
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m4_pwm2_pins_a: m4-pwm2-0 {
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pins {
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pinmux = <STM32_PINMUX('A', 3, RSVD)>; /* TIM2_CH4 */
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};
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};
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m4_pwm3_pins_a: m4-pwm3-0 {
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pins {
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pinmux = <STM32_PINMUX('C', 7, RSVD)>; /* TIM3_CH2 */
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};
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};
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m4_pwm4_pins_a: m4-pwm4-0 {
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pins {
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pinmux = <STM32_PINMUX('D', 14, RSVD)>, /* TIM4_CH3 */
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<STM32_PINMUX('D', 15, RSVD)>; /* TIM4_CH4 */
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};
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};
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m4_pwm4_pins_b: m4-pwm4-1 {
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pins {
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pinmux = <STM32_PINMUX('D', 13, RSVD)>; /* TIM4_CH2 */
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};
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};
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m4_pwm5_pins_a: m4-pwm5-0 {
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pins {
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pinmux = <STM32_PINMUX('H', 11, RSVD)>; /* TIM5_CH2 */
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};
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};
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m4_pwm8_pins_a: m4-pwm8-0 {
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pins {
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pinmux = <STM32_PINMUX('I', 2, RSVD)>; /* TIM8_CH4 */
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};
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};
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||
|
|
|
||
|
|
m4_pwm12_pins_a: m4-pwm12-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('H', 6, RSVD)>; /* TIM12_CH1 */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_qspi_bk1_pins_a: m4-qspi-bk1-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('F', 8, RSVD)>, /* QSPI_BK1_IO0 */
|
||
|
|
<STM32_PINMUX('F', 9, RSVD)>, /* QSPI_BK1_IO1 */
|
||
|
|
<STM32_PINMUX('F', 7, RSVD)>, /* QSPI_BK1_IO2 */
|
||
|
|
<STM32_PINMUX('F', 6, RSVD)>, /* QSPI_BK1_IO3 */
|
||
|
|
<STM32_PINMUX('B', 6, RSVD)>; /* QSPI_BK1_NCS */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_qspi_bk2_pins_a: m4-qspi-bk2-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('H', 2, RSVD)>, /* QSPI_BK2_IO0 */
|
||
|
|
<STM32_PINMUX('H', 3, RSVD)>, /* QSPI_BK2_IO1 */
|
||
|
|
<STM32_PINMUX('G', 10, RSVD)>, /* QSPI_BK2_IO2 */
|
||
|
|
<STM32_PINMUX('G', 7, RSVD)>, /* QSPI_BK2_IO3 */
|
||
|
|
<STM32_PINMUX('C', 0, RSVD)>; /* QSPI_BK2_NCS */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_qspi_clk_pins_a: m4-qspi-clk-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('F', 10, RSVD)>; /* QSPI_CLK */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_rtc_out2_rmp_pins_a: m4-rtc-out2-rmp-pins-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('I', 8, RSVD)>; /* RTC_OUT2_RMP */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_sai2a_pins_a: m4-sai2a-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('I', 5, RSVD)>, /* SAI2_SCK_A */
|
||
|
|
<STM32_PINMUX('I', 6, RSVD)>, /* SAI2_SD_A */
|
||
|
|
<STM32_PINMUX('I', 7, RSVD)>, /* SAI2_FS_A */
|
||
|
|
<STM32_PINMUX('E', 0, RSVD)>; /* SAI2_MCLK_A */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_sai2b_pins_a: m4-sai2b-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('E', 12, RSVD)>, /* SAI2_SCK_B */
|
||
|
|
<STM32_PINMUX('E', 13, RSVD)>, /* SAI2_FS_B */
|
||
|
|
<STM32_PINMUX('E', 14, RSVD)>, /* SAI2_MCLK_B */
|
||
|
|
<STM32_PINMUX('F', 11, RSVD)>; /* SAI2_SD_B */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_sai2b_pins_b: m4-sai2b-2 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('F', 11, RSVD)>; /* SAI2_SD_B */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_sai4a_pins_a: m4-sai4a-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('B', 5, RSVD)>; /* SAI4_SD_A */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_sdmmc1_b4_pins_a: m4-sdmmc1-b4-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('C', 8, RSVD)>, /* SDMMC1_D0 */
|
||
|
|
<STM32_PINMUX('C', 9, RSVD)>, /* SDMMC1_D1 */
|
||
|
|
<STM32_PINMUX('C', 10, RSVD)>, /* SDMMC1_D2 */
|
||
|
|
<STM32_PINMUX('C', 11, RSVD)>, /* SDMMC1_D3 */
|
||
|
|
<STM32_PINMUX('D', 2, RSVD)>, /* SDMMC1_CMD */
|
||
|
|
<STM32_PINMUX('C', 12, RSVD)>; /* SDMMC1_CK */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_sdmmc1_dir_pins_a: m4-sdmmc1-dir-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('F', 2, RSVD)>, /* SDMMC1_D0DIR */
|
||
|
|
<STM32_PINMUX('C', 7, RSVD)>, /* SDMMC1_D123DIR */
|
||
|
|
<STM32_PINMUX('B', 9, RSVD)>, /* SDMMC1_CDIR */
|
||
|
|
<STM32_PINMUX('E', 4, RSVD)>; /* SDMMC1_CKIN */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_sdmmc2_b4_pins_a: m4-sdmmc2-b4-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('B', 14, RSVD)>, /* SDMMC2_D0 */
|
||
|
|
<STM32_PINMUX('B', 15, RSVD)>, /* SDMMC2_D1 */
|
||
|
|
<STM32_PINMUX('B', 3, RSVD)>, /* SDMMC2_D2 */
|
||
|
|
<STM32_PINMUX('B', 4, RSVD)>, /* SDMMC2_D3 */
|
||
|
|
<STM32_PINMUX('G', 6, RSVD)>, /* SDMMC2_CMD */
|
||
|
|
<STM32_PINMUX('E', 3, RSVD)>; /* SDMMC2_CK */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_sdmmc2_b4_pins_b: m4-sdmmc2-b4-1 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('B', 14, RSVD)>, /* SDMMC2_D0 */
|
||
|
|
<STM32_PINMUX('B', 15, RSVD)>, /* SDMMC2_D1 */
|
||
|
|
<STM32_PINMUX('B', 3, RSVD)>, /* SDMMC2_D2 */
|
||
|
|
<STM32_PINMUX('B', 4, RSVD)>, /* SDMMC2_D3 */
|
||
|
|
<STM32_PINMUX('G', 6, RSVD)>, /* SDMMC2_CMD */
|
||
|
|
<STM32_PINMUX('E', 3, RSVD)>; /* SDMMC2_CK */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_sdmmc2_d47_pins_a: m4-sdmmc2-d47-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('A', 8, RSVD)>, /* SDMMC2_D4 */
|
||
|
|
<STM32_PINMUX('A', 9, RSVD)>, /* SDMMC2_D5 */
|
||
|
|
<STM32_PINMUX('E', 5, RSVD)>, /* SDMMC2_D6 */
|
||
|
|
<STM32_PINMUX('D', 3, RSVD)>; /* SDMMC2_D7 */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_sdmmc3_b4_pins_a: m4-sdmmc3-b4-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('F', 0, RSVD)>, /* SDMMC3_D0 */
|
||
|
|
<STM32_PINMUX('F', 4, RSVD)>, /* SDMMC3_D1 */
|
||
|
|
<STM32_PINMUX('F', 5, RSVD)>, /* SDMMC3_D2 */
|
||
|
|
<STM32_PINMUX('D', 7, RSVD)>, /* SDMMC3_D3 */
|
||
|
|
<STM32_PINMUX('F', 1, RSVD)>, /* SDMMC3_CMD */
|
||
|
|
<STM32_PINMUX('G', 15, RSVD)>; /* SDMMC3_CK */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_spdifrx_pins_a: m4-spdifrx-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('G', 12, RSVD)>; /* SPDIF_IN1 */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_spi4_pins_a: m4-spi4-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('E', 12, RSVD)>, /* SPI4_SCK */
|
||
|
|
<STM32_PINMUX('E', 14, RSVD)>, /* SPI4_MOSI */
|
||
|
|
<STM32_PINMUX('E', 13, RSVD)>; /* SPI4_MISO */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_spi5_pins_a: m4-spi5-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('F', 7, RSVD)>, /* SPI5_SCK */
|
||
|
|
<STM32_PINMUX('F', 9, RSVD)>, /* SPI5_MOSI */
|
||
|
|
<STM32_PINMUX('F', 8, RSVD)>; /* SPI5_MISO */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_stusb1600_pins_a: m4-stusb1600-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('I', 11, RSVD)>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_uart4_pins_a: m4-uart4-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('G', 11, RSVD)>, /* UART4_TX */
|
||
|
|
<STM32_PINMUX('B', 2, RSVD)>; /* UART4_RX */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_uart7_pins_a: m4-uart7-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('E', 8, RSVD)>, /* USART7_TX */
|
||
|
|
<STM32_PINMUX('E', 7, RSVD)>; /* USART7_RX */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_usart2_pins_a: m4-usart2-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('D', 5, RSVD)>, /* USART2_TX */
|
||
|
|
<STM32_PINMUX('D', 4, RSVD)>, /* USART2_RTS */
|
||
|
|
<STM32_PINMUX('D', 6, RSVD)>, /* USART2_RX */
|
||
|
|
<STM32_PINMUX('D', 3, RSVD)>; /* USART2_CTS_NSS */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_usart3_pins_a: m4-usart3-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('B', 10, RSVD)>, /* USART3_TX */
|
||
|
|
<STM32_PINMUX('G', 8, RSVD)>, /* USART3_RTS */
|
||
|
|
<STM32_PINMUX('B', 12, RSVD)>, /* USART3_RX */
|
||
|
|
<STM32_PINMUX('I', 10, RSVD)>; /* USART3_CTS_NSS */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_usart3_pins_b: m4-usart3-1 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('B', 10, RSVD)>, /* USART3_TX */
|
||
|
|
<STM32_PINMUX('G', 8, RSVD)>, /* USART3_RTS */
|
||
|
|
<STM32_PINMUX('B', 12, RSVD)>, /* USART3_RX */
|
||
|
|
<STM32_PINMUX('B', 13, RSVD)>; /* USART3_CTS_NSS */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_usbotg_hs_pins_a: m4-usbotg_hs-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('A', 10, RSVD)>; /* OTG_ID */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_usbotg_fs_dp_dm_pins_a: m4-usbotg-fs-dp-dm-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('A', 11, RSVD)>, /* OTG_FS_DM */
|
||
|
|
<STM32_PINMUX('A', 12, RSVD)>; /* OTG_FS_DP */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&pinctrl_z {
|
||
|
|
m4_i2c4_pins_a: m4-i2c4-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('Z', 4, RSVD)>, /* I2C4_SCL */
|
||
|
|
<STM32_PINMUX('Z', 5, RSVD)>; /* I2C4_SDA */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
m4_spi1_pins_a: m4-spi1-0 {
|
||
|
|
pins {
|
||
|
|
pinmux = <STM32_PINMUX('Z', 0, RSVD)>, /* SPI1_SCK */
|
||
|
|
<STM32_PINMUX('Z', 2, RSVD)>, /* SPI1_MOSI */
|
||
|
|
<STM32_PINMUX('Z', 1, RSVD)>; /* SPI1_MISO */
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|