363 lines
8.6 KiB
Plaintext
363 lines
8.6 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include <dt-bindings/pinctrl/k3.h>
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#include <dt-bindings/dma/k3-udma.h>
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#include <dt-bindings/net/ti-dp83867.h>
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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};
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aliases {
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serial2 = &main_uart0;
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ethernet0 = &cpsw_port1;
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};
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};
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&cbass_main{
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u-boot,dm-spl;
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sdhci1: sdhci@04FA0000 {
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compatible = "ti,am654-sdhci-5.1";
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reg = <0x0 0x4FA0000 0x0 0x1000>,
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<0x0 0x4FB0000 0x0 0x400>;
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clocks = <&k3_clks 48 1>;
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power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
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max-frequency = <25000000>;
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ti,otap-del-sel = <0x2>;
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ti,trm-icp = <0x8>;
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};
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};
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&cbass_mcu {
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u-boot,dm-spl;
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navss_mcu: navss-mcu {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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ti,sci-dev-id = <119>;
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mcu_ringacc: ringacc@2b800000 {
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compatible = "ti,am654-navss-ringacc";
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reg = <0x0 0x2b800000 0x0 0x400000>,
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<0x0 0x2b000000 0x0 0x400000>,
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<0x0 0x28590000 0x0 0x100>,
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<0x0 0x2a500000 0x0 0x40000>;
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reg-names = "rt", "fifos",
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"proxy_gcfg", "proxy_target";
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ti,num-rings = <286>;
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ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
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ti,dma-ring-reset-quirk;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <195>;
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};
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mcu_udmap: udmap@285c0000 {
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compatible = "ti,k3-navss-udmap";
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reg = <0x0 0x285c0000 0x0 0x100>,
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<0x0 0x2a800000 0x0 0x40000>,
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<0x0 0x2aa00000 0x0 0x40000>;
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reg-names = "gcfg", "rchanrt", "tchanrt";
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#dma-cells = <3>;
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ti,ringacc = <&mcu_ringacc>;
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ti,psil-base = <0x6000>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <194>;
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ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
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<0x2>; /* TX_CHAN */
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ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
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<0x4>; /* RX_CHAN */
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ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
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dma-coherent;
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};
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};
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mcu_conf: scm_conf@40f00000 {
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compatible = "syscon";
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reg = <0x0 0x40f00000 0x0 0x20000>;
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};
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mcu_cpsw: cpsw_nuss@046000000 {
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compatible = "ti,am654-cpsw-nuss";
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#address-cells = <2>;
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#size-cells = <2>;
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reg = <0x0 0x46000000 0x0 0x200000>;
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reg-names = "cpsw_nuss";
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ranges;
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dma-coherent;
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clocks = <&k3_clks 5 10>;
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clock-names = "fck";
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power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
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ti,psil-base = <0x7000>;
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dmas = <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_TX>,
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<&mcu_udmap &mcu_cpsw 1 UDMA_DIR_TX>,
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<&mcu_udmap &mcu_cpsw 2 UDMA_DIR_TX>,
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<&mcu_udmap &mcu_cpsw 3 UDMA_DIR_TX>,
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<&mcu_udmap &mcu_cpsw 4 UDMA_DIR_TX>,
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<&mcu_udmap &mcu_cpsw 5 UDMA_DIR_TX>,
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<&mcu_udmap &mcu_cpsw 6 UDMA_DIR_TX>,
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<&mcu_udmap &mcu_cpsw 7 UDMA_DIR_TX>,
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<&mcu_udmap &mcu_cpsw 0 UDMA_DIR_RX>;
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dma-names = "tx0", "tx1", "tx2", "tx3",
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"tx4", "tx5", "tx6", "tx7",
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"rx";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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host: host@0 {
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reg = <0>;
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ti,label = "host";
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};
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cpsw_port1: port@1 {
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reg = <1>;
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ti,mac-only;
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ti,label = "port1";
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ti,syscon-efuse = <&mcu_conf 0x200>;
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};
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};
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davinci_mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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bus_freq = <1000000>;
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};
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ti,psil-config0 {
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linux,udma-mode = <UDMA_PKT_MODE>;
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statictr-type = <PSIL_STATIC_TR_NONE>;
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ti,needs-epib;
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ti,psd-size = <16>;
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};
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ti,psil-config1 {
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linux,udma-mode = <UDMA_PKT_MODE>;
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statictr-type = <PSIL_STATIC_TR_NONE>;
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ti,needs-epib;
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ti,psd-size = <16>;
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};
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ti,psil-config2 {
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linux,udma-mode = <UDMA_PKT_MODE>;
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statictr-type = <PSIL_STATIC_TR_NONE>;
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ti,needs-epib;
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ti,psd-size = <16>;
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};
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ti,psil-config3 {
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linux,udma-mode = <UDMA_PKT_MODE>;
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statictr-type = <PSIL_STATIC_TR_NONE>;
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ti,needs-epib;
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ti,psd-size = <16>;
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};
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ti,psil-config4 {
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linux,udma-mode = <UDMA_PKT_MODE>;
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statictr-type = <PSIL_STATIC_TR_NONE>;
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ti,needs-epib;
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ti,psd-size = <16>;
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};
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ti,psil-config5 {
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linux,udma-mode = <UDMA_PKT_MODE>;
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statictr-type = <PSIL_STATIC_TR_NONE>;
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ti,needs-epib;
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ti,psd-size = <16>;
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};
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ti,psil-config6 {
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linux,udma-mode = <UDMA_PKT_MODE>;
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statictr-type = <PSIL_STATIC_TR_NONE>;
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ti,needs-epib;
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ti,psd-size = <16>;
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};
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ti,psil-config7 {
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linux,udma-mode = <UDMA_PKT_MODE>;
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statictr-type = <PSIL_STATIC_TR_NONE>;
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ti,needs-epib;
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ti,psd-size = <16>;
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};
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};
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};
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&cbass_wakeup {
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u-boot,dm-spl;
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};
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&secure_proxy_main {
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u-boot,dm-spl;
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};
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&dmsc {
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u-boot,dm-spl;
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k3_sysreset: sysreset-controller {
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compatible = "ti,sci-sysreset";
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u-boot,dm-spl;
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};
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};
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&k3_pds {
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u-boot,dm-spl;
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};
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&k3_clks {
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u-boot,dm-spl;
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};
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&k3_reset {
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u-boot,dm-spl;
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};
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&wkup_pmx0 {
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u-boot,dm-spl;
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wkup_i2c0_pins_default {
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u-boot,dm-spl;
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};
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};
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&main_pmx0 {
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u-boot,dm-spl;
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main_uart0_pins_default: main_uart0_pins_default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
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AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
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AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
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AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
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>;
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u-boot,dm-spl;
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};
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main_mmc0_pins_default: main_mmc0_pins_default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
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AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
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AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
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AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
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AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
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AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
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AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
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AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
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AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
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AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
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AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
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AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
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>;
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u-boot,dm-spl;
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};
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main_mmc1_pins_default: main_mmc1_pins_default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
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AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
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AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
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AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
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AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
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AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
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AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
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AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
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>;
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u-boot,dm-spl;
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};
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};
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&main_pmx1 {
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u-boot,dm-spl;
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};
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&wkup_pmx0 {
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mcu_cpsw_pins_default: mcu_cpsw_pins_default {
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pinctrl-single,pins = <
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AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
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AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
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AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
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AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
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AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
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AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
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AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
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AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
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AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
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AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
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AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
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AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
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>;
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};
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mcu_mdio_pins_default: mcu_mdio1_pins_default {
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pinctrl-single,pins = <
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AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
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AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
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>;
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};
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};
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&main_uart0 {
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u-boot,dm-spl;
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart0_pins_default>;
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status = "okay";
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};
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&sdhci0 {
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u-boot,dm-spl;
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};
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&sdhci1 {
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u-boot,dm-spl;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&main_mmc1_pins_default>;
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sdhci-caps-mask = <0x7 0x0>;
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ti,driver-strength-ohm = <50>;
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};
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|
|
&mcu_cpsw {
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&davinci_mdio {
|
||
|
|
phy0: ethernet-phy@0 {
|
||
|
|
reg = <0>;
|
||
|
|
/* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
|
||
|
|
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||
|
|
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&cpsw_port1 {
|
||
|
|
phy-mode = "rgmii-rxid";
|
||
|
|
phy-handle = <&phy0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&mcu_cpsw {
|
||
|
|
reg = <0x0 0x46000000 0x0 0x200000>,
|
||
|
|
<0x0 0x40f00200 0x0 0x2>;
|
||
|
|
reg-names = "cpsw_nuss", "mac_efuse";
|
||
|
|
|
||
|
|
cpsw-phy-sel@40f04040 {
|
||
|
|
compatible = "ti,am654-cpsw-phy-sel";
|
||
|
|
reg= <0x0 0x40f04040 0x0 0x4>;
|
||
|
|
reg-names = "gmii-sel";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&wkup_i2c0 {
|
||
|
|
u-boot,dm-spl;
|
||
|
|
};
|