89 lines
1.4 KiB
Plaintext
89 lines
1.4 KiB
Plaintext
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#include <dt-bindings/clock/ast2500-scu.h>
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#include <dt-bindings/reset/ast2500-reset.h>
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#include "ast2500.dtsi"
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/ {
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scu: clock-controller@1e6e2000 {
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compatible = "aspeed,ast2500-scu";
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reg = <0x1e6e2000 0x1000>;
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u-boot,dm-pre-reloc;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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rst: reset-controller {
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u-boot,dm-pre-reloc;
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compatible = "aspeed,ast2500-reset";
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aspeed,wdt = <&wdt1>;
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#reset-cells = <1>;
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};
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sdrammc: sdrammc@1e6e0000 {
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u-boot,dm-pre-reloc;
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compatible = "aspeed,ast2500-sdrammc";
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reg = <0x1e6e0000 0x174
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0x1e6e0200 0x1d4 >;
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#reset-cells = <1>;
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clocks = <&scu PLL_MPLL>;
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resets = <&rst AST_RESET_SDRAM>;
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};
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ahb {
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u-boot,dm-pre-reloc;
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apb {
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u-boot,dm-pre-reloc;
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sdhci0: sdhci@1e740100 {
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compatible = "aspeed,ast2500-sdhci";
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reg = <0x1e740100>;
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#reset-cells = <1>;
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clocks = <&scu BCLK_SDCLK>;
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resets = <&rst AST_RESET_SDIO>;
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};
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sdhci1: sdhci@1e740200 {
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compatible = "aspeed,ast2500-sdhci";
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reg = <0x1e740200>;
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#reset-cells = <1>;
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clocks = <&scu BCLK_SDCLK>;
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resets = <&rst AST_RESET_SDIO>;
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};
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};
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};
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};
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&uart1 {
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clocks = <&scu PCLK_UART1>;
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};
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&uart2 {
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clocks = <&scu PCLK_UART2>;
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};
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&uart3 {
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clocks = <&scu PCLK_UART3>;
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};
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&uart4 {
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clocks = <&scu PCLK_UART4>;
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};
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&uart5 {
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clocks = <&scu PCLK_UART5>;
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};
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&timer {
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u-boot,dm-pre-reloc;
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};
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&mac0 {
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clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
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};
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&mac1 {
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clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
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};
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