25 lines
625 B
Plaintext
25 lines
625 B
Plaintext
|
config RISCV_NDS
|
||
|
|
bool
|
||
|
|
select ARCH_EARLY_INIT_R
|
||
|
|
imply CPU
|
||
|
|
imply CPU_RISCV
|
||
|
|
imply RISCV_TIMER
|
||
|
|
imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
|
||
|
|
imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
|
||
|
|
imply SPL_CPU_SUPPORT
|
||
|
|
imply SPL_OPENSBI
|
||
|
|
imply SPL_LOAD_FIT
|
||
|
|
help
|
||
|
|
Run U-Boot on AndeStar V5 platforms and use some specific features
|
||
|
|
which are provided by Andes Technology AndeStar V5 families.
|
||
|
|
|
||
|
|
if RISCV_NDS
|
||
|
|
|
||
|
|
config RISCV_NDS_CACHE
|
||
|
|
bool "AndeStar V5 families specific cache support"
|
||
|
|
depends on RISCV_MMODE || SPL_RISCV_MMODE
|
||
|
|
help
|
||
|
|
Provide Andes Technology AndeStar V5 families specific cache support.
|
||
|
|
|
||
|
|
endif
|