99 lines
1.6 KiB
ArmAsm
99 lines
1.6 KiB
ArmAsm
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Startup Code for MIPS32 XBURST CPU-core
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*
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* Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
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*/
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#include <config.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/cacheops.h>
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#include <asm/cache.h>
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#include <mach/jz4780.h>
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.set noreorder
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.globl _start
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.text
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_start:
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#ifdef CONFIG_SPL_BUILD
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/* magic value ("MSPL") */
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.word 0x4d53504c
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/* Invalidate BTB */
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mfc0 t0, CP0_CONFIG, 7
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nop
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ori t0, 2
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mtc0 t0, CP0_CONFIG, 7
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nop
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/*
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* CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
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*/
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li t0, 0x0040FC04
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mtc0 t0, CP0_STATUS
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/* CAUSE register */
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/* IV=1, use the specical interrupt vector (0x200) */
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li t1, 0x00800000
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mtc0 t1, CP0_CAUSE
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#ifdef CONFIG_SOC_JZ4780
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/* enable bridge radical mode */
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la t0, CPM_BASE
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lw t1, 0x24(t0)
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ori t1, t1, 0x22
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sw t1, 0x24(t0)
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#endif
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/* Set up stack */
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li sp, CONFIG_SPL_STACK
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b board_init_f
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nop
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#ifdef CONFIG_SOC_JZ4780
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.globl enable_caches
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.ent enable_caches
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enable_caches:
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mtc0 zero, CP0_TAGLO
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mtc0 zero, CP0_TAGHI
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li t0, KSEG0
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addu t1, t0, CONFIG_SYS_DCACHE_SIZE
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1:
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cache INDEX_STORE_TAG_D, 0(t0)
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bne t0, t1, 1b
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addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE
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li t0, KSEG0
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addu t1, t0, CONFIG_SYS_ICACHE_SIZE
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2:
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cache INDEX_STORE_TAG_I, 0(t0)
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bne t0, t1, 2b
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addiu t0, t0, CONFIG_SYS_CACHELINE_SIZE
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/* Invalidate BTB */
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mfc0 t0, CP0_CONFIG, 7
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nop
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ori t0, 2
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mtc0 t0, CP0_CONFIG, 7
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nop
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/* Enable caches */
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li t0, CONF_CM_CACHABLE_NONCOHERENT
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mtc0 t0, CP0_CONFIG
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nop
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jr ra
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nop
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.end enable_caches
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#endif /* CONFIG_SOC_JZ4780 */
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#endif /* !CONFIG_SPL_BUILD */
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