333 lines
9.3 KiB
C
333 lines
9.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
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* Based on Atheros LSDK/QSDK
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include <mach/ar71xx_regs.h>
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#include <mach/ath79.h>
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#define DDR_CTRL_UPD_EMR3S BIT(5)
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#define DDR_CTRL_UPD_EMR2S BIT(4)
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#define DDR_CTRL_PRECHARGE BIT(3)
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#define DDR_CTRL_AUTO_REFRESH BIT(2)
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#define DDR_CTRL_UPD_EMRS BIT(1)
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#define DDR_CTRL_UPD_MRS BIT(0)
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#define DDR_REFRESH_EN BIT(14)
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#define DDR_REFRESH_M 0x3ff
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#define DDR_REFRESH(x) ((x) & 0x3ff)
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#define DDR_REFRESH_VAL_25M (DDR_REFRESH_EN | DDR_REFRESH(390))
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#define DDR_REFRESH_VAL_40M (DDR_REFRESH_EN | DDR_REFRESH(624))
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#define DDR_TRAS_S 0
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#define DDR_TRAS_M 0x1f
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#define DDR_TRAS(x) ((x) << DDR_TRAS_S)
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#define DDR_TRCD_M 0xf
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#define DDR_TRCD_S 5
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#define DDR_TRCD(x) ((x) << DDR_TRCD_S)
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#define DDR_TRP_M 0xf
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#define DDR_TRP_S 9
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#define DDR_TRP(x) ((x) << DDR_TRP_S)
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#define DDR_TRRD_M 0xf
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#define DDR_TRRD_S 13
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#define DDR_TRRD(x) ((x) << DDR_TRRD_S)
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#define DDR_TRFC_M 0x7f
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#define DDR_TRFC_S 17
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#define DDR_TRFC(x) ((x) << DDR_TRFC_S)
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#define DDR_TMRD_M 0xf
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#define DDR_TMRD_S 23
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#define DDR_TMRD(x) ((x) << DDR_TMRD_S)
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#define DDR_CAS_L_M 0x17
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#define DDR_CAS_L_S 27
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#define DDR_CAS_L(x) (((x) & DDR_CAS_L_M) << DDR_CAS_L_S)
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#define DDR_OPEN BIT(30)
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#define DDR_CONF_REG_VAL (DDR_TRAS(16) | DDR_TRCD(6) | \
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DDR_TRP(6) | DDR_TRRD(4) | \
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DDR_TRFC(30) | DDR_TMRD(15) | \
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DDR_CAS_L(7) | DDR_OPEN)
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#define DDR_BURST_LEN_S 0
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#define DDR_BURST_LEN_M 0xf
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#define DDR_BURST_LEN(x) ((x) << DDR_BURST_LEN_S)
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#define DDR_BURST_TYPE BIT(4)
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#define DDR_CNTL_OE_EN BIT(5)
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#define DDR_PHASE_SEL BIT(6)
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#define DDR_CKE BIT(7)
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#define DDR_TWR_S 8
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#define DDR_TWR_M 0xf
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#define DDR_TWR(x) ((x) << DDR_TWR_S)
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#define DDR_TRTW_S 12
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#define DDR_TRTW_M 0x1f
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#define DDR_TRTW(x) ((x) << DDR_TRTW_S)
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#define DDR_TRTP_S 17
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#define DDR_TRTP_M 0xf
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#define DDR_TRTP(x) ((x) << DDR_TRTP_S)
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#define DDR_TWTR_S 21
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#define DDR_TWTR_M 0x1f
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#define DDR_TWTR(x) ((x) << DDR_TWTR_S)
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#define DDR_G_OPEN_L_S 26
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#define DDR_G_OPEN_L_M 0xf
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#define DDR_G_OPEN_L(x) ((x) << DDR_G_OPEN_L_S)
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#define DDR_HALF_WIDTH_LOW BIT(31)
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#define DDR_CONF2_REG_VAL (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
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DDR_CKE | DDR_TWR(6) | DDR_TRTW(14) | \
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DDR_TRTP(8) | DDR_TWTR(14) | \
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DDR_G_OPEN_L(7) | DDR_HALF_WIDTH_LOW)
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#define DDR2_CONF_TWL_S 10
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#define DDR2_CONF_TWL_M 0xf
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#define DDR2_CONF_TWL(x) (((x) & DDR2_CONF_TWL_M) << DDR2_CONF_TWL_S)
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#define DDR2_CONF_ODT BIT(9)
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#define DDR2_CONF_TFAW_S 2
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#define DDR2_CONF_TFAW_M 0x3f
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#define DDR2_CONF_TFAW(x) (((x) & DDR2_CONF_TFAW_M) << DDR2_CONF_TFAW_S)
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#define DDR2_CONF_EN BIT(0)
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#define DDR2_CONF_VAL (DDR2_CONF_TWL(2) | DDR2_CONF_ODT | \
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DDR2_CONF_TFAW(22) | DDR2_CONF_EN)
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#define DDR1_EXT_MODE_VAL 0x02
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#define DDR2_EXT_MODE_VAL 0x402
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#define DDR2_EXT_MODE_OCD_VAL 0x382
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#define DDR1_MODE_DLL_VAL 0x133
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#define DDR2_MODE_DLL_VAL 0x100
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#define DDR1_MODE_VAL 0x33
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#define DDR2_MODE_VAL 0xa33
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#define DDR_TAP_VAL0 0x08
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#define DDR_TAP_VAL1 0x09
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void ddr_init(void)
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{
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void __iomem *regs;
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u32 val;
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regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
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MAP_NOCACHE);
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writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
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writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
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val = ath79_get_bootstrap();
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if (val & AR933X_BOOTSTRAP_DDR2) {
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/* AHB maximum timeout */
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writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
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/* Enable DDR2 */
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writel(DDR2_CONF_VAL, regs + AR933X_DDR_REG_DDR2_CONFIG);
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/* Precharge All */
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writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
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/* Disable High Temperature Self-Refresh, Full Array */
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writel(0x00, regs + AR933X_DDR_REG_EMR2);
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/* Extended Mode Register 2 Set (EMR2S) */
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writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
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writel(0x00, regs + AR933X_DDR_REG_EMR3);
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/* Extended Mode Register 3 Set (EMR3S) */
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writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
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/* Enable DLL, Full strength, ODT Disabled */
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writel(0x00, regs + AR71XX_DDR_REG_EMR);
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/* Extended Mode Register Set (EMRS) */
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writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
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/* Reset DLL */
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writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
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/* Mode Register Set (MRS) */
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writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
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/* Precharge All */
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writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
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/* Auto Refresh */
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writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
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writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
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/* Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8 */
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writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
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/* Mode Register Set (MRS) */
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writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
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/* Enable OCD defaults, Enable DLL, Reduced Drive Strength */
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writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
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/* Extended Mode Register Set (EMRS) */
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writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
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/* OCD exit, Enable DLL, Enable /DQS, Reduced Drive Strength */
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writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
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/* Extended Mode Register Set (EMRS) */
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writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
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/* Refresh time control */
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if (val & AR933X_BOOTSTRAP_REF_CLK_40)
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writel(DDR_REFRESH_VAL_40M, regs +
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AR71XX_DDR_REG_REFRESH);
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else
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writel(DDR_REFRESH_VAL_25M, regs +
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AR71XX_DDR_REG_REFRESH);
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/* DQS 0 Tap Control */
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writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0);
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/* DQS 1 Tap Control */
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writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1);
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/* For 16-bit DDR */
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writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
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} else {
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/* AHB maximum timeout */
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writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
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/* Precharge All */
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writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
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/* Reset DLL, Burst Length 8, CAS Latency 3 */
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writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
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/* Forces an MRS update cycle in DDR */
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writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
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/* Enable DLL, Full strength */
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writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
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/* Extended Mode Register Set (EMRS) */
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writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
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/* Precharge All */
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writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
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/* Normal DLL, Burst Length 8, CAS Latency 3 */
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writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
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/* Mode Register Set (MRS) */
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writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
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/* Refresh time control */
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if (val & AR933X_BOOTSTRAP_REF_CLK_40)
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writel(DDR_REFRESH_VAL_40M, regs +
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AR71XX_DDR_REG_REFRESH);
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else
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writel(DDR_REFRESH_VAL_25M, regs +
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AR71XX_DDR_REG_REFRESH);
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/* DQS 0 Tap Control */
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writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0);
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/* DQS 1 Tap Control */
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writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1);
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/* For 16-bit DDR */
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writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
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}
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}
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void ddr_tap_tuning(void)
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{
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void __iomem *regs;
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u32 *addr_k0, *addr_k1, *addr;
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u32 val, tap, upper, lower;
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int i, j, dir, err, done;
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regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
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MAP_NOCACHE);
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/* Init memory pattern */
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addr = (void *)CKSEG0ADDR(0x2000);
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for (i = 0; i < 256; i++) {
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val = 0;
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for (j = 0; j < 8; j++) {
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if (i & (1 << j)) {
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if (j % 2)
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val |= 0xffff0000;
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else
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val |= 0x0000ffff;
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}
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if (j % 2) {
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*addr++ = val;
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val = 0;
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}
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}
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}
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err = 0;
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done = 0;
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dir = 1;
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tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
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val = tap;
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upper = tap;
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lower = tap;
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while (!done) {
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err = 0;
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/* Update new DDR tap value */
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writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
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writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
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/* Compare DDR with cache */
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for (i = 0; i < 2; i++) {
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addr_k1 = (void *)CKSEG1ADDR(0x2000);
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addr_k0 = (void *)CKSEG0ADDR(0x2000);
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addr = (void *)CKSEG0ADDR(0x3000);
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while (addr_k0 < addr) {
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if (*addr_k1++ != *addr_k0++) {
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err = 1;
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break;
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}
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}
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if (err)
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break;
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}
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if (err) {
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/* Save upper/lower threshold if error */
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if (dir) {
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dir = 0;
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val--;
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upper = val;
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val = tap;
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} else {
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val++;
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lower = val;
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done = 1;
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}
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} else {
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/* Try the next value until limitation */
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if (dir) {
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if (val < 0x20) {
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val++;
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} else {
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dir = 0;
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upper = val;
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val = tap;
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}
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} else {
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if (!val) {
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lower = val;
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done = 1;
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} else {
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val--;
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}
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}
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}
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}
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/* compute an intermediate value and write back */
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val = (upper + lower) / 2;
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writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
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val++;
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writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
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}
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