103 lines
3.5 KiB
C
103 lines
3.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* timer.h -- ColdFire internal TIMER support defines.
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*/
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/****************************************************************************/
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#ifndef timer_h
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#define timer_h
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/****************************************************************************/
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/****************************************************************************/
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/* Timer structure */
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/****************************************************************************/
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/* DMA Timer module registers */
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typedef struct dtimer_ctrl {
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#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
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defined(CONFIG_M5272) || defined(CONFIG_M5307)
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u16 tmr; /* 0x00 Mode register */
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u16 res1; /* 0x02 */
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u16 trr; /* 0x04 Reference register */
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u16 res2; /* 0x06 */
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u16 tcr; /* 0x08 Capture register */
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u16 res3; /* 0x0A */
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u16 tcn; /* 0x0C Counter register */
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u16 res4; /* 0x0E */
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u8 res6; /* 0x10 */
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u8 ter; /* 0x11 Event register */
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u16 res7; /* 0x12 */
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#else
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u16 tmr; /* 0x00 Mode register */
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u8 txmr; /* 0x02 Extended Mode register */
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u8 ter; /* 0x03 Event register */
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u32 trr; /* 0x04 Reference register */
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u32 tcr; /* 0x08 Capture register */
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u32 tcn; /* 0x0C Counter register */
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#endif
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} dtmr_t;
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/*Programmable Interrupt Timer */
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typedef struct pit_ctrl {
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u16 pcsr; /* 0x00 Control and Status Register */
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u16 pmr; /* 0x02 Modulus Register */
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u16 pcntr; /* 0x04 Count Register */
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} pit_t;
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/*********************************************************************
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* DMA Timers (DTIM)
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*********************************************************************/
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/* Bit definitions and macros for DTMR */
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#define DTIM_DTMR_RST (0x0001) /* Reset */
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#define DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) /* Input clock source */
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#define DTIM_DTMR_FRR (0x0008) /* Free run/restart */
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#define DTIM_DTMR_ORRI (0x0010) /* Output reference request/interrupt enable */
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#define DTIM_DTMR_OM (0x0020) /* Output Mode */
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#define DTIM_DTMR_CE(x) (((x)&0x0003)<<6) /* Capture Edge */
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#define DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) /* Prescaler value */
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#define DTIM_DTMR_RST_EN (0x0001)
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#define DTIM_DTMR_RST_RST (0x0000)
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#define DTIM_DTMR_CE_ANY (0x00C0)
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#define DTIM_DTMR_CE_FALL (0x0080)
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#define DTIM_DTMR_CE_RISE (0x0040)
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#define DTIM_DTMR_CE_NONE (0x0000)
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#define DTIM_DTMR_CLK_DTIN (0x0006)
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#define DTIM_DTMR_CLK_DIV16 (0x0004)
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#define DTIM_DTMR_CLK_DIV1 (0x0002)
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#define DTIM_DTMR_CLK_STOP (0x0000)
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/* Bit definitions and macros for DTXMR */
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#define DTIM_DTXMR_MODE16 (0x01) /* Increment Mode */
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#define DTIM_DTXMR_DMAEN (0x80) /* DMA request */
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/* Bit definitions and macros for DTER */
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#define DTIM_DTER_CAP (0x01) /* Capture event */
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#define DTIM_DTER_REF (0x02) /* Output reference event */
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/*********************************************************************
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*
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* Programmable Interrupt Timer Modules (PIT)
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*
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*********************************************************************/
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/* Bit definitions and macros for PCSR */
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#define PIT_PCSR_EN (0x0001)
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#define PIT_PCSR_RLD (0x0002)
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#define PIT_PCSR_PIF (0x0004)
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#define PIT_PCSR_PIE (0x0008)
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#define PIT_PCSR_OVW (0x0010)
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#define PIT_PCSR_HALTED (0x0020)
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#define PIT_PCSR_DOZE (0x0040)
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#define PIT_PCSR_PRE(x) (((x)&0x000F)<<8)
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/* Bit definitions and macros for PMR */
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#define PIT_PMR_PM(x) (x)
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/* Bit definitions and macros for PCNTR */
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#define PIT_PCNTR_PC(x) (x)
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/****************************************************************************/
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#endif /* timer_h */
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