346 lines
7.9 KiB
C
346 lines
7.9 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015-2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <common.h>
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#include <stdio.h>
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#include <linux/io.h>
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#include <linux/printk.h>
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#include <linux/sizes.h>
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#include "../soc-info.h"
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#include "ddrmphy-regs.h"
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/* Select either decimal or hexadecimal */
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#if 1
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#define PRINTF_FORMAT "%2d"
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#else
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#define PRINTF_FORMAT "%02x"
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#endif
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/* field separator */
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#define FS " "
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#define ptr_to_uint(p) ((unsigned int)(unsigned long)(p))
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#define UNIPHIER_MAX_NR_DDRMPHY 3
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struct uniphier_ddrmphy_param {
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unsigned int soc_id;
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unsigned int nr_phy;
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struct {
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resource_size_t base;
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unsigned int nr_zq;
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unsigned int nr_dx;
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} phy[UNIPHIER_MAX_NR_DDRMPHY];
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};
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static const struct uniphier_ddrmphy_param uniphier_ddrmphy_param[] = {
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{
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.soc_id = UNIPHIER_PXS2_ID,
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.nr_phy = 3,
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.phy = {
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{ .base = 0x5b830000, .nr_zq = 3, .nr_dx = 4, },
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{ .base = 0x5ba30000, .nr_zq = 3, .nr_dx = 4, },
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{ .base = 0x5bc30000, .nr_zq = 2, .nr_dx = 2, },
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},
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},
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{
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.soc_id = UNIPHIER_LD6B_ID,
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.nr_phy = 3,
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.phy = {
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{ .base = 0x5b830000, .nr_zq = 3, .nr_dx = 4, },
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{ .base = 0x5ba30000, .nr_zq = 3, .nr_dx = 4, },
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{ .base = 0x5bc30000, .nr_zq = 2, .nr_dx = 2, },
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},
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},
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};
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UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_ddrmphy_param, uniphier_ddrmphy_param)
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static void print_bdl(void __iomem *reg, int n)
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{
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u32 val = readl(reg);
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int i;
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for (i = 0; i < n; i++)
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printf(FS PRINTF_FORMAT, (val >> i * 8) & 0x1f);
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}
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static void dump_loop(const struct uniphier_ddrmphy_param *param,
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void (*callback)(void __iomem *))
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{
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void __iomem *phy_base, *dx_base;
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int phy, dx;
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for (phy = 0; phy < param->nr_phy; phy++) {
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phy_base = ioremap(param->phy[phy].base, SZ_4K);
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dx_base = phy_base + MPHY_DX_BASE;
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for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
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printf("PHY%dDX%d:", phy, dx);
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(*callback)(dx_base);
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dx_base += MPHY_DX_STRIDE;
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printf("\n");
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}
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iounmap(phy_base);
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}
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}
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static void zq_dump(const struct uniphier_ddrmphy_param *param)
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{
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void __iomem *phy_base, *zq_base;
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u32 val;
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int phy, zq, i;
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printf("\n--- Impedance Data ---\n");
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printf(" ZPD ZPU OPD OPU ZDV ODV\n");
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for (phy = 0; phy < param->nr_phy; phy++) {
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phy_base = ioremap(param->phy[phy].base, SZ_4K);
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zq_base = phy_base + MPHY_ZQ_BASE;
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for (zq = 0; zq < param->phy[phy].nr_zq; zq++) {
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printf("PHY%dZQ%d:", phy, zq);
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val = readl(zq_base + MPHY_ZQ_DR);
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for (i = 0; i < 4; i++) {
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printf(FS PRINTF_FORMAT, val & 0x7f);
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val >>= 7;
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}
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val = readl(zq_base + MPHY_ZQ_PR);
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for (i = 0; i < 2; i++) {
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printf(FS PRINTF_FORMAT, val & 0xf);
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val >>= 4;
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}
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zq_base += MPHY_ZQ_STRIDE;
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printf("\n");
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}
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iounmap(phy_base);
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}
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}
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static void __wbdl_dump(void __iomem *dx_base)
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{
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print_bdl(dx_base + MPHY_DX_BDLR0, 4);
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print_bdl(dx_base + MPHY_DX_BDLR1, 4);
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print_bdl(dx_base + MPHY_DX_BDLR2, 2);
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printf(FS "(+" PRINTF_FORMAT ")",
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readl(dx_base + MPHY_DX_LCDLR1) & 0xff);
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}
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static void wbdl_dump(const struct uniphier_ddrmphy_param *param)
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{
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printf("\n--- Write Bit Delay Line ---\n");
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printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
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dump_loop(param, &__wbdl_dump);
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}
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static void __rbdl_dump(void __iomem *dx_base)
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{
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print_bdl(dx_base + MPHY_DX_BDLR3, 4);
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print_bdl(dx_base + MPHY_DX_BDLR4, 4);
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print_bdl(dx_base + MPHY_DX_BDLR5, 1);
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printf(FS "(+" PRINTF_FORMAT ")",
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(readl(dx_base + MPHY_DX_LCDLR1) >> 8) & 0xff);
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printf(FS "(+" PRINTF_FORMAT ")",
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(readl(dx_base + MPHY_DX_LCDLR1) >> 16) & 0xff);
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}
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static void rbdl_dump(const struct uniphier_ddrmphy_param *param)
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{
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printf("\n--- Read Bit Delay Line ---\n");
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printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD) (RDQSND)\n");
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dump_loop(param, &__rbdl_dump);
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}
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static void __wld_dump(void __iomem *dx_base)
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{
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int rank;
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u32 lcdlr0 = readl(dx_base + MPHY_DX_LCDLR0);
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u32 gtr = readl(dx_base + MPHY_DX_GTR);
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for (rank = 0; rank < 4; rank++) {
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u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
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u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
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printf(FS PRINTF_FORMAT "%sT", wld,
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wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
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}
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}
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static void wld_dump(const struct uniphier_ddrmphy_param *param)
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{
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printf("\n--- Write Leveling Delay ---\n");
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printf(" Rank0 Rank1 Rank2 Rank3\n");
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dump_loop(param, &__wld_dump);
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}
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static void __dqsgd_dump(void __iomem *dx_base)
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{
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int rank;
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u32 lcdlr2 = readl(dx_base + MPHY_DX_LCDLR2);
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u32 gtr = readl(dx_base + MPHY_DX_GTR);
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for (rank = 0; rank < 4; rank++) {
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u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
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u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
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printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
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}
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}
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static void dqsgd_dump(const struct uniphier_ddrmphy_param *param)
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{
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printf("\n--- DQS Gating Delay ---\n");
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printf(" Rank0 Rank1 Rank2 Rank3\n");
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dump_loop(param, &__dqsgd_dump);
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}
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static void __mdl_dump(void __iomem *dx_base)
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{
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int i;
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u32 mdl = readl(dx_base + MPHY_DX_MDLR);
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for (i = 0; i < 3; i++)
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printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
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}
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static void mdl_dump(const struct uniphier_ddrmphy_param *param)
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{
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printf("\n--- Master Delay Line ---\n");
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printf(" IPRD TPRD MDLD\n");
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dump_loop(param, &__mdl_dump);
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}
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#define REG_DUMP(x) \
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{ int ofst = MPHY_ ## x; void __iomem *reg = phy_base + ofst; \
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printf("%3d: %-10s: %p : %08x\n", \
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ofst >> MPHY_SHIFT, #x, reg, readl(reg)); }
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#define DX_REG_DUMP(dx, x) \
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{ int ofst = MPHY_DX_BASE + MPHY_DX_STRIDE * (dx) + \
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MPHY_DX_## x; \
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void __iomem *reg = phy_base + ofst; \
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printf("%3d: DX%d%-7s: %p : %08x\n", \
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ofst >> MPHY_SHIFT, (dx), #x, reg, readl(reg)); }
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static void reg_dump(const struct uniphier_ddrmphy_param *param)
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{
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void __iomem *phy_base;
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int phy, dx;
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printf("\n--- DDR Multi PHY registers ---\n");
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for (phy = 0; phy < param->nr_phy; phy++) {
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phy_base = ioremap(param->phy[phy].base, SZ_4K);
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printf("== PHY%d (base: %08x) ==\n", phy,
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ptr_to_uint(phy_base));
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printf(" No: Name : Address : Data\n");
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REG_DUMP(RIDR);
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REG_DUMP(PIR);
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REG_DUMP(PGCR0);
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REG_DUMP(PGCR1);
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REG_DUMP(PGCR2);
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REG_DUMP(PGCR3);
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REG_DUMP(PGSR0);
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REG_DUMP(PGSR1);
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REG_DUMP(PLLCR);
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REG_DUMP(PTR0);
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REG_DUMP(PTR1);
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REG_DUMP(PTR2);
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REG_DUMP(PTR3);
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REG_DUMP(PTR4);
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REG_DUMP(ACMDLR);
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REG_DUMP(ACBDLR0);
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REG_DUMP(DXCCR);
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REG_DUMP(DSGCR);
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REG_DUMP(DCR);
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REG_DUMP(DTPR0);
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REG_DUMP(DTPR1);
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REG_DUMP(DTPR2);
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REG_DUMP(DTPR3);
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REG_DUMP(MR0);
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REG_DUMP(MR1);
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REG_DUMP(MR2);
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REG_DUMP(MR3);
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for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
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DX_REG_DUMP(dx, GCR0);
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DX_REG_DUMP(dx, GCR1);
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DX_REG_DUMP(dx, GCR2);
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DX_REG_DUMP(dx, GCR3);
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DX_REG_DUMP(dx, GTR);
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}
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iounmap(phy_base);
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}
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}
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static int do_ddrm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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const struct uniphier_ddrmphy_param *param;
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char *cmd;
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param = uniphier_get_ddrmphy_param();
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if (!param) {
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pr_err("unsupported SoC\n");
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return CMD_RET_FAILURE;
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}
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if (argc == 1)
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cmd = "all";
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else
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cmd = argv[1];
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if (!strcmp(cmd, "zq") || !strcmp(cmd, "all"))
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zq_dump(param);
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if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
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wbdl_dump(param);
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if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
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rbdl_dump(param);
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if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
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wld_dump(param);
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if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
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dqsgd_dump(param);
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if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
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mdl_dump(param);
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if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
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reg_dump(param);
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return CMD_RET_SUCCESS;
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}
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U_BOOT_CMD(
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ddrm, 2, 1, do_ddrm,
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"UniPhier DDR Multi PHY parameters dumper",
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"- dump all of the following\n"
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"ddrm zq - dump Impedance Data\n"
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"ddrm wbdl - dump Write Bit Delay\n"
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"ddrm rbdl - dump Read Bit Delay\n"
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"ddrm wld - dump Write Leveling\n"
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"ddrm dqsgd - dump DQS Gating Delay\n"
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"ddrm mdl - dump Master Delay Line\n"
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"ddrm reg - dump registers\n"
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);
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