40 lines
925 B
C
40 lines
925 B
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
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*/
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/* Tegra cache routines */
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch-tegra/ap.h>
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#if IS_ENABLED(CONFIG_TEGRA_GP_PADCTRL)
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#include <asm/arch/gp_padctrl.h>
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#endif
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#ifndef CONFIG_ARM64
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void config_cache(void)
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{
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u32 reg = 0;
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/* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
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asm volatile(
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"mrc p15, 0, r0, c1, c0, 1\n"
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"orr r0, r0, #0x41\n"
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"mcr p15, 0, r0, c1, c0, 1\n");
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/* Currently, only Tegra114+ needs this L2 cache change to boot Linux */
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if (tegra_get_chip() < CHIPID_TEGRA114)
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return;
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/*
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* Systems with an architectural L2 cache must not use the PL310.
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* Config L2CTLR here for a data RAM latency of 3 cycles.
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*/
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asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
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reg &= ~7;
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reg |= 2;
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asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
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}
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#endif
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