407 lines
11 KiB
C
407 lines
11 KiB
C
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/*
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* clock_ti816x.c
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*
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* Clocks for TI816X based boards
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*
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* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
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* Antoine Tenart, <atenart@adeneo-embedded.com>
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*
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* Based on TI-PSP-04.00.02.14 :
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*
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* Copyright (C) 2009, Texas Instruments, Incorporated
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#define CM_PLL_BASE (CTRL_BASE + 0x0400)
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/* Main PLL */
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#define MAIN_N 64
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#define MAIN_P 0x1
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#define MAIN_INTFREQ1 0x8
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#define MAIN_FRACFREQ1 0x800000
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#define MAIN_MDIV1 0x2
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#define MAIN_INTFREQ2 0xE
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#define MAIN_FRACFREQ2 0x0
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#define MAIN_MDIV2 0x1
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#define MAIN_INTFREQ3 0x8
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#define MAIN_FRACFREQ3 0xAAAAB0
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#define MAIN_MDIV3 0x3
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#define MAIN_INTFREQ4 0x9
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#define MAIN_FRACFREQ4 0x55554F
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#define MAIN_MDIV4 0x3
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#define MAIN_INTFREQ5 0x9
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#define MAIN_FRACFREQ5 0x374BC6
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#define MAIN_MDIV5 0xC
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#define MAIN_MDIV6 0x48
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#define MAIN_MDIV7 0x4
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/* DDR PLL */
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#define DDR_N 59
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#define DDR_P 0x1
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#define DDR_MDIV1 0x2
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#define DDR_INTFREQ2 0x8
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#define DDR_FRACFREQ2 0xD99999
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#define DDR_MDIV2 0x1E
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#define DDR_INTFREQ3 0x8
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#define DDR_FRACFREQ3 0x0
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#define DDR_MDIV3 0x4
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#define DDR_INTFREQ4 0xE /* Expansion DDR clk */
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#define DDR_FRACFREQ4 0x0
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#define DDR_MDIV4 0x4
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#define DDR_INTFREQ5 0xE /* Expansion DDR clk */
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#define DDR_FRACFREQ5 0x0
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#define DDR_MDIV5 0x4
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#define CONTROL_STATUS (CTRL_BASE + 0x40)
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#define DDR_RCD (CTRL_BASE + 0x070C)
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#define CM_TIMER1_CLKSEL (PRCM_BASE + 0x390)
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#define CM_ALWON_CUST_EFUSE_CLKCTRL (PRCM_BASE + 0x1628)
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#define INTCPS_SYSCONFIG 0x48200010
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#define CM_SYSCLK10_CLKSEL 0x48180324
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struct cm_pll {
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unsigned int mainpll_ctrl; /* offset 0x400 */
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unsigned int mainpll_pwd;
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unsigned int mainpll_freq1;
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unsigned int mainpll_div1;
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unsigned int mainpll_freq2;
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unsigned int mainpll_div2;
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unsigned int mainpll_freq3;
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unsigned int mainpll_div3;
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unsigned int mainpll_freq4;
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unsigned int mainpll_div4;
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unsigned int mainpll_freq5;
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unsigned int mainpll_div5;
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unsigned int resv0[1];
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unsigned int mainpll_div6;
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unsigned int resv1[1];
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unsigned int mainpll_div7;
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unsigned int ddrpll_ctrl; /* offset 0x440 */
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unsigned int ddrpll_pwd;
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unsigned int resv2[1];
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unsigned int ddrpll_div1;
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unsigned int ddrpll_freq2;
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unsigned int ddrpll_div2;
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unsigned int ddrpll_freq3;
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unsigned int ddrpll_div3;
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unsigned int ddrpll_freq4;
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unsigned int ddrpll_div4;
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unsigned int ddrpll_freq5;
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unsigned int ddrpll_div5;
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unsigned int videopll_ctrl; /* offset 0x470 */
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unsigned int videopll_pwd;
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unsigned int videopll_freq1;
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unsigned int videopll_div1;
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unsigned int videopll_freq2;
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unsigned int videopll_div2;
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unsigned int videopll_freq3;
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unsigned int videopll_div3;
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unsigned int resv3[4];
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unsigned int audiopll_ctrl; /* offset 0x4A0 */
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unsigned int audiopll_pwd;
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unsigned int resv4[2];
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unsigned int audiopll_freq2;
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unsigned int audiopll_div2;
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unsigned int audiopll_freq3;
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unsigned int audiopll_div3;
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unsigned int audiopll_freq4;
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unsigned int audiopll_div4;
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unsigned int audiopll_freq5;
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unsigned int audiopll_div5;
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};
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const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
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const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
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const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE;
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const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
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void enable_dmm_clocks(void)
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{
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writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
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/* Wait for dmm to be fully functional, including OCP */
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while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0)
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;
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}
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void enable_emif_clocks(void)
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{
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writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
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writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
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writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
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writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
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/* Wait for clocks to be active */
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while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
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;
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/* Wait for emif0 to be fully functional, including OCP */
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while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0)
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;
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/* Wait for emif1 to be fully functional, including OCP */
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while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0)
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;
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}
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/* assume delay is aprox at least 1us */
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static void ddr_delay(int d)
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{
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int i;
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/*
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* read a control register.
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* this is a bit more delay and cannot be optimized by the compiler
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* assuming one read takes 200 cycles and A8 is runing 1 GHz
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* somewhat conservative setting
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*/
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for (i = 0; i < 50*d; i++)
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readl(CONTROL_STATUS);
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}
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static void main_pll_init_ti816x(void)
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{
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u32 main_pll_ctrl = 0;
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/* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
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main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
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main_pll_ctrl &= 0xFFFFFFFB;
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main_pll_ctrl |= BIT(2);
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writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
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/* Enable PLL by setting BIT3 in its ctrl reg */
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main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
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main_pll_ctrl &= 0xFFFFFFF7;
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main_pll_ctrl |= BIT(3);
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writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
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/* Write the values of N,P in the CTRL reg */
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main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
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main_pll_ctrl &= 0xFF;
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main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8);
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writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
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/* Power up clock1-7 */
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writel(0x0, &cmpll->mainpll_pwd);
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/* Program the freq and divider values for clock1-7 */
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writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1),
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&cmpll->mainpll_freq1);
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writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1);
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writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2),
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&cmpll->mainpll_freq2);
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writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2);
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writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3),
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&cmpll->mainpll_freq3);
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writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3);
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writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4),
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&cmpll->mainpll_freq4);
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writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4);
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writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5),
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&cmpll->mainpll_freq5);
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writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5);
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writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6);
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writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7);
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/* Wait for PLL to lock */
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while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7))
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;
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/* Put the PLL in normal mode, disable bypass */
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main_pll_ctrl = readl(&cmpll->mainpll_ctrl);
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main_pll_ctrl &= 0xFFFFFFFB;
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writel(main_pll_ctrl, &cmpll->mainpll_ctrl);
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}
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static void ddr_pll_bypass_ti816x(void)
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{
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u32 ddr_pll_ctrl = 0;
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/* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */
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ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
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ddr_pll_ctrl &= 0xFFFFFFFB;
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ddr_pll_ctrl |= BIT(2);
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writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
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}
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static void ddr_pll_init_ti816x(void)
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{
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u32 ddr_pll_ctrl = 0;
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/* Enable PLL by setting BIT3 in its ctrl reg */
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ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
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ddr_pll_ctrl &= 0xFFFFFFF7;
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ddr_pll_ctrl |= BIT(3);
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writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
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/* Write the values of N,P in the CTRL reg */
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ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl);
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ddr_pll_ctrl &= 0xFF;
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ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8);
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writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl);
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ddr_delay(10);
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/* Power up clock1-5 */
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writel(0x0, &cmpll->ddrpll_pwd);
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/* Program the freq and divider values for clock1-3 */
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writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
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ddr_delay(1);
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writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1);
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writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2),
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&cmpll->ddrpll_freq2);
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writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2);
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writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
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ddr_delay(1);
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writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3);
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ddr_delay(1);
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writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
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&cmpll->ddrpll_freq3);
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ddr_delay(1);
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writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3),
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&cmpll->ddrpll_freq3);
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ddr_delay(5);
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/* Wait for PLL to lock */
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while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7))
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;
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/* Power up RCD */
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writel(BIT(0), DDR_RCD);
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}
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static void peripheral_enable(void)
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{
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/* Wake-up the l3_slow clock */
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writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
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/*
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* Note on Timers:
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* There are 8 timers(0-7) out of which timer 0 is a secure timer.
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* Timer 0 mux should not be changed
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*
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* To access the timer registers we need the to be
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* enabled which is what we do in the first step
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*/
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/* Enable timer1 */
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writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl);
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/* Select timer1 clock to be CLKIN (27MHz) */
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writel(BIT(1), CM_TIMER1_CLKSEL);
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/* Wait for timer1 to be ON-ACTIVE */
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while (((readl(&cmalwon->l3slowclkstctrl)
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& (0x80000<<1))>>20) != 1)
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;
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/* Wait for timer1 to be enabled */
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while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0)
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;
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/* Active posted mode */
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writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54));
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while (readl(DM_TIMER1_BASE + 0x10) & BIT(0))
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;
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/* Start timer1 */
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writel(BIT(0), (DM_TIMER1_BASE + 0x38));
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/* eFuse */
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writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL);
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while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN)
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;
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/* Enable gpio0 */
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writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl);
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while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN)
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|
;
|
||
|
|
writel((BIT(1) | BIT(8)), &cmalwon->gpio0clkctrl);
|
||
|
|
|
||
|
|
/* Enable gpio1 */
|
||
|
|
writel(PRCM_MOD_EN, &cmalwon->gpio1clkctrl);
|
||
|
|
while (readl(&cmalwon->gpio1clkctrl) != PRCM_MOD_EN)
|
||
|
|
;
|
||
|
|
writel((BIT(1) | BIT(8)), &cmalwon->gpio1clkctrl);
|
||
|
|
|
||
|
|
/* Enable spi */
|
||
|
|
writel(PRCM_MOD_EN, &cmalwon->spiclkctrl);
|
||
|
|
while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN)
|
||
|
|
;
|
||
|
|
|
||
|
|
/* Enable i2c0 */
|
||
|
|
writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl);
|
||
|
|
while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN)
|
||
|
|
;
|
||
|
|
|
||
|
|
/* Enable ethernet0 */
|
||
|
|
writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
|
||
|
|
writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
|
||
|
|
writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
|
||
|
|
|
||
|
|
/* Enable hsmmc */
|
||
|
|
writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl);
|
||
|
|
while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN)
|
||
|
|
;
|
||
|
|
}
|
||
|
|
|
||
|
|
void setup_clocks_for_console(void)
|
||
|
|
{
|
||
|
|
/* Fix ROM code bug - from TI-PSP-04.00.02.14 */
|
||
|
|
writel(0x0, CM_SYSCLK10_CLKSEL);
|
||
|
|
|
||
|
|
ddr_pll_bypass_ti816x();
|
||
|
|
|
||
|
|
/* Enable uart0-2 */
|
||
|
|
writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
|
||
|
|
while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
|
||
|
|
;
|
||
|
|
writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl);
|
||
|
|
while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN)
|
||
|
|
;
|
||
|
|
writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl);
|
||
|
|
while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN)
|
||
|
|
;
|
||
|
|
while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
|
||
|
|
;
|
||
|
|
}
|
||
|
|
|
||
|
|
void setup_early_clocks(void)
|
||
|
|
{
|
||
|
|
setup_clocks_for_console();
|
||
|
|
}
|
||
|
|
|
||
|
|
void prcm_init(void)
|
||
|
|
{
|
||
|
|
/* Enable the control */
|
||
|
|
writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
|
||
|
|
|
||
|
|
main_pll_init_ti816x();
|
||
|
|
ddr_pll_init_ti816x();
|
||
|
|
|
||
|
|
/*
|
||
|
|
* With clk freqs setup to desired values,
|
||
|
|
* enable the required peripherals
|
||
|
|
*/
|
||
|
|
peripheral_enable();
|
||
|
|
}
|