581 lines
14 KiB
C
581 lines
14 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* board.c
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*
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* Common board functions for AM33XX based boards
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*/
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#include <common.h>
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#include <dm.h>
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#include <debug_uart.h>
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#include <errno.h>
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#include <ns16550.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/i2c.h>
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#include <asm/arch/mem.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <asm/omap_common.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include <linux/errno.h>
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#include <linux/compiler.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <linux/usb/musb.h>
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#include <asm/omap_musb.h>
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#include <asm/davinci_rtc.h>
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#define AM43XX_EMIF_BASE 0x4C000000
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#define AM43XX_SDRAM_CONFIG_OFFSET 0x8
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#define AM43XX_SDRAM_TYPE_MASK 0xE0000000
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#define AM43XX_SDRAM_TYPE_SHIFT 29
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#define AM43XX_SDRAM_TYPE_DDR3 3
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#define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC
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#define AM43XX_RDWRLVLFULL_START 0x80000000
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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sdram_init();
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#endif
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size(
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(void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_MAX_RAM_BANK_SIZE);
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = gd->ram_size;
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return 0;
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}
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#if !CONFIG_IS_ENABLED(OF_CONTROL)
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static const struct ns16550_platdata am33xx_serial[] = {
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{ .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
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.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
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# ifdef CONFIG_SYS_NS16550_COM2
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{ .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
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.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
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# ifdef CONFIG_SYS_NS16550_COM3
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{ .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
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.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
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{ .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
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.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
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{ .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
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.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
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{ .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
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.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
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# endif
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# endif
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};
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U_BOOT_DEVICES(am33xx_uarts) = {
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{ "ns16550_serial", &am33xx_serial[0] },
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# ifdef CONFIG_SYS_NS16550_COM2
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{ "ns16550_serial", &am33xx_serial[1] },
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# ifdef CONFIG_SYS_NS16550_COM3
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{ "ns16550_serial", &am33xx_serial[2] },
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{ "ns16550_serial", &am33xx_serial[3] },
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{ "ns16550_serial", &am33xx_serial[4] },
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{ "ns16550_serial", &am33xx_serial[5] },
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# endif
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# endif
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};
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#ifdef CONFIG_DM_I2C
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static const struct omap_i2c_platdata am33xx_i2c[] = {
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{ I2C_BASE1, 100000, OMAP_I2C_REV_V2},
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{ I2C_BASE2, 100000, OMAP_I2C_REV_V2},
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{ I2C_BASE3, 100000, OMAP_I2C_REV_V2},
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};
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U_BOOT_DEVICES(am33xx_i2c) = {
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{ "i2c_omap", &am33xx_i2c[0] },
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{ "i2c_omap", &am33xx_i2c[1] },
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{ "i2c_omap", &am33xx_i2c[2] },
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};
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#endif
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#ifdef CONFIG_DM_GPIO
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static const struct omap_gpio_platdata am33xx_gpio[] = {
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{ 0, AM33XX_GPIO0_BASE },
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{ 1, AM33XX_GPIO1_BASE },
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{ 2, AM33XX_GPIO2_BASE },
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{ 3, AM33XX_GPIO3_BASE },
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#ifdef CONFIG_AM43XX
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{ 4, AM33XX_GPIO4_BASE },
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{ 5, AM33XX_GPIO5_BASE },
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#endif
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};
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U_BOOT_DEVICES(am33xx_gpios) = {
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{ "gpio_omap", &am33xx_gpio[0] },
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{ "gpio_omap", &am33xx_gpio[1] },
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{ "gpio_omap", &am33xx_gpio[2] },
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{ "gpio_omap", &am33xx_gpio[3] },
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#ifdef CONFIG_AM43XX
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{ "gpio_omap", &am33xx_gpio[4] },
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{ "gpio_omap", &am33xx_gpio[5] },
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#endif
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};
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#endif
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#endif
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#ifndef CONFIG_DM_GPIO
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static const struct gpio_bank gpio_bank_am33xx[] = {
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{ (void *)AM33XX_GPIO0_BASE },
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{ (void *)AM33XX_GPIO1_BASE },
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{ (void *)AM33XX_GPIO2_BASE },
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{ (void *)AM33XX_GPIO3_BASE },
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#ifdef CONFIG_AM43XX
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{ (void *)AM33XX_GPIO4_BASE },
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{ (void *)AM33XX_GPIO5_BASE },
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#endif
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};
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const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
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#endif
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#if defined(CONFIG_MMC_OMAP_HS)
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int cpu_mmc_init(bd_t *bis)
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{
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int ret;
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ret = omap_mmc_init(0, 0, 0, -1, -1);
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if (ret)
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return ret;
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return omap_mmc_init(1, 0, 0, -1, -1);
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}
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#endif
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/*
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* RTC only with DDR in self-refresh mode magic value, checked against during
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* boot to see if we have a valid config. This should be in sync with the value
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* that will be in drivers/soc/ti/pm33xx.c.
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*/
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#define RTC_MAGIC_VAL 0x8cd0
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/* Board type field bit shift for RTC only with DDR in self-refresh mode */
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#define RTC_BOARD_TYPE_SHIFT 16
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/* AM33XX has two MUSB controllers which can be host or gadget */
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#if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
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(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
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(!CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL)) && \
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(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_MUSB_NEW_SUPPORT))
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static struct musb_hdrc_config musb_config = {
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.multipoint = 1,
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.dyn_fifo = 1,
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.num_eps = 16,
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.ram_bits = 12,
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};
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#if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL)
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static struct ti_musb_platdata usb0 = {
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.base = (void *)USB0_OTG_BASE,
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.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
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.plat = {
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.config = &musb_config,
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.power = 50,
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.platform_ops = &musb_dsps_ops,
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},
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};
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static struct ti_musb_platdata usb1 = {
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.base = (void *)USB1_OTG_BASE,
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.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
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.plat = {
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.config = &musb_config,
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.power = 50,
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.platform_ops = &musb_dsps_ops,
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},
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};
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U_BOOT_DEVICES(am33xx_usbs) = {
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#if CONFIG_AM335X_USB0_MODE == MUSB_PERIPHERAL
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{ "ti-musb-peripheral", &usb0 },
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#elif CONFIG_AM335X_USB0_MODE == MUSB_HOST
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{ "ti-musb-host", &usb0 },
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#endif
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#if CONFIG_AM335X_USB1_MODE == MUSB_PERIPHERAL
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{ "ti-musb-peripheral", &usb1 },
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#elif CONFIG_AM335X_USB1_MODE == MUSB_HOST
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{ "ti-musb-host", &usb1 },
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#endif
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};
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int arch_misc_init(void)
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{
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return 0;
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}
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#else
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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/* USB 2.0 PHY Control */
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#define CM_PHY_PWRDN (1 << 0)
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#define CM_PHY_OTG_PWRDN (1 << 1)
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#define OTGVDET_EN (1 << 19)
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#define OTGSESSENDEN (1 << 20)
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static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
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{
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if (on) {
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clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
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OTGVDET_EN | OTGSESSENDEN);
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} else {
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clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
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}
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}
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#ifdef CONFIG_AM335X_USB0
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static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
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{
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am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
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}
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struct omap_musb_board_data otg0_board_data = {
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.set_phy_power = am33xx_otg0_set_phy_power,
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};
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static struct musb_hdrc_platform_data otg0_plat = {
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.mode = CONFIG_AM335X_USB0_MODE,
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.config = &musb_config,
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.power = 50,
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.platform_ops = &musb_dsps_ops,
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.board_data = &otg0_board_data,
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};
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#endif
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#ifdef CONFIG_AM335X_USB1
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static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
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{
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am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
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}
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struct omap_musb_board_data otg1_board_data = {
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.set_phy_power = am33xx_otg1_set_phy_power,
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};
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static struct musb_hdrc_platform_data otg1_plat = {
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.mode = CONFIG_AM335X_USB1_MODE,
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.config = &musb_config,
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.power = 50,
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.platform_ops = &musb_dsps_ops,
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.board_data = &otg1_board_data,
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};
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#endif
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int arch_misc_init(void)
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{
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#ifdef CONFIG_AM335X_USB0
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musb_register(&otg0_plat, &otg0_board_data,
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(void *)USB0_OTG_BASE);
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#endif
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#ifdef CONFIG_AM335X_USB1
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musb_register(&otg1_plat, &otg1_board_data,
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(void *)USB1_OTG_BASE);
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#endif
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return 0;
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}
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#endif
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#else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
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int arch_misc_init(void)
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{
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struct udevice *dev;
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int ret;
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ret = uclass_first_device(UCLASS_MISC, &dev);
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if (ret || !dev)
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return ret;
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#if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
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ret = usb_ether_init();
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if (ret) {
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pr_err("USB ether init failed\n");
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return ret;
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}
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#endif
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return 0;
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}
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#endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
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(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
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static void rtc32k_unlock(struct davinci_rtc *rtc)
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{
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/*
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* Unlock the RTC's registers. For more details please see the
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* RTC_SS section of the TRM. In order to unlock we need to
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* write these specific values (keys) in this order.
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*/
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writel(RTC_KICK0R_WE, &rtc->kick0r);
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writel(RTC_KICK1R_WE, &rtc->kick1r);
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}
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#endif
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#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
|
||
|
|
/*
|
||
|
|
* Write contents of the RTC_SCRATCH1 register based on board type
|
||
|
|
* Two things are passed
|
||
|
|
* on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
|
||
|
|
* control gets to kernel, kernel reads the scratchpad register and gets to
|
||
|
|
* know that bootloader has rtc_only support.
|
||
|
|
*
|
||
|
|
* Second important thing is the board type (16:31). This is needed in the
|
||
|
|
* rtc_only boot where in we want to avoid costly i2c reads to eeprom to
|
||
|
|
* identify the board type and we go ahead and copy the board strings to
|
||
|
|
* am43xx_board_name.
|
||
|
|
*/
|
||
|
|
void update_rtc_magic(void)
|
||
|
|
{
|
||
|
|
struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
|
||
|
|
u32 magic = RTC_MAGIC_VAL;
|
||
|
|
|
||
|
|
magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
|
||
|
|
|
||
|
|
rtc32k_unlock(rtc);
|
||
|
|
|
||
|
|
/* write magic */
|
||
|
|
writel(magic, &rtc->scratch1);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/*
|
||
|
|
* In the case of non-SPL based booting we'll want to call these
|
||
|
|
* functions a tiny bit later as it will require gd to be set and cleared
|
||
|
|
* and that's not true in s_init in this case so we cannot do it there.
|
||
|
|
*/
|
||
|
|
int board_early_init_f(void)
|
||
|
|
{
|
||
|
|
set_mux_conf_regs();
|
||
|
|
prcm_init();
|
||
|
|
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
|
||
|
|
update_rtc_magic();
|
||
|
|
#endif
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This function is the place to do per-board things such as ramp up the
|
||
|
|
* MPU clock frequency.
|
||
|
|
*/
|
||
|
|
__weak void am33xx_spl_board_init(void)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
|
||
|
|
static void rtc32k_enable(void)
|
||
|
|
{
|
||
|
|
struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
|
||
|
|
|
||
|
|
rtc32k_unlock(rtc);
|
||
|
|
|
||
|
|
/* Enable the RTC 32K OSC by setting bits 3 and 6. */
|
||
|
|
writel((1 << 3) | (1 << 6), &rtc->osc);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static void uart_soft_reset(void)
|
||
|
|
{
|
||
|
|
struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
|
||
|
|
u32 regval;
|
||
|
|
|
||
|
|
regval = readl(&uart_base->uartsyscfg);
|
||
|
|
regval |= UART_RESET;
|
||
|
|
writel(regval, &uart_base->uartsyscfg);
|
||
|
|
while ((readl(&uart_base->uartsyssts) &
|
||
|
|
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
|
||
|
|
;
|
||
|
|
|
||
|
|
/* Disable smart idle */
|
||
|
|
regval = readl(&uart_base->uartsyscfg);
|
||
|
|
regval |= UART_SMART_IDLE_EN;
|
||
|
|
writel(regval, &uart_base->uartsyscfg);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void watchdog_disable(void)
|
||
|
|
{
|
||
|
|
struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
|
||
|
|
|
||
|
|
writel(0xAAAA, &wdtimer->wdtwspr);
|
||
|
|
while (readl(&wdtimer->wdtwwps) != 0x0)
|
||
|
|
;
|
||
|
|
writel(0x5555, &wdtimer->wdtwspr);
|
||
|
|
while (readl(&wdtimer->wdtwwps) != 0x0)
|
||
|
|
;
|
||
|
|
}
|
||
|
|
|
||
|
|
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
|
||
|
|
/*
|
||
|
|
* Check if we are executing rtc-only + DDR mode, and resume from it if needed
|
||
|
|
*/
|
||
|
|
static void rtc_only(void)
|
||
|
|
{
|
||
|
|
struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
|
||
|
|
struct prm_device_inst *prm_device =
|
||
|
|
(struct prm_device_inst *)PRM_DEVICE_INST;
|
||
|
|
|
||
|
|
u32 scratch1, sdrc;
|
||
|
|
void (*resume_func)(void);
|
||
|
|
|
||
|
|
scratch1 = readl(&rtc->scratch1);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
|
||
|
|
* written to this register when we want to wake up from RTC only
|
||
|
|
* with DDR in self-refresh mode. Contents of the RTC_SCRATCH1:
|
||
|
|
* bits 0-15: RTC_MAGIC_VAL
|
||
|
|
* bits 16-31: board type (needed for sdram_init)
|
||
|
|
*/
|
||
|
|
if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
|
||
|
|
return;
|
||
|
|
|
||
|
|
rtc32k_unlock(rtc);
|
||
|
|
|
||
|
|
/* Clear RTC magic */
|
||
|
|
writel(0, &rtc->scratch1);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Update board type based on value stored on RTC_SCRATCH1, this
|
||
|
|
* is done so that we don't need to read the board type from eeprom
|
||
|
|
* over i2c bus which is expensive
|
||
|
|
*/
|
||
|
|
rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we
|
||
|
|
* are resuming from self-refresh. This avoids an unnecessary re-init
|
||
|
|
* of the DDR. The re-init takes time and we would need to wait for
|
||
|
|
* it to complete before accessing DDR to avoid L3 NOC errors.
|
||
|
|
*/
|
||
|
|
writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);
|
||
|
|
|
||
|
|
rtc_only_prcm_init();
|
||
|
|
sdram_init();
|
||
|
|
|
||
|
|
/* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */
|
||
|
|
/* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */
|
||
|
|
sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET);
|
||
|
|
|
||
|
|
sdrc &= AM43XX_SDRAM_TYPE_MASK;
|
||
|
|
sdrc >>= AM43XX_SDRAM_TYPE_SHIFT;
|
||
|
|
|
||
|
|
if (sdrc == AM43XX_SDRAM_TYPE_DDR3) {
|
||
|
|
writel(AM43XX_RDWRLVLFULL_START,
|
||
|
|
AM43XX_EMIF_BASE +
|
||
|
|
AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
|
||
|
|
mdelay(1);
|
||
|
|
|
||
|
|
am43xx_wait:
|
||
|
|
sdrc = readl(AM43XX_EMIF_BASE +
|
||
|
|
AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET);
|
||
|
|
if (sdrc == AM43XX_RDWRLVLFULL_START)
|
||
|
|
goto am43xx_wait;
|
||
|
|
}
|
||
|
|
|
||
|
|
resume_func = (void *)readl(&rtc->scratch0);
|
||
|
|
if (resume_func)
|
||
|
|
resume_func();
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
void s_init(void)
|
||
|
|
{
|
||
|
|
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
|
||
|
|
rtc_only();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
void early_system_init(void)
|
||
|
|
{
|
||
|
|
/*
|
||
|
|
* The ROM will only have set up sufficient pinmux to allow for the
|
||
|
|
* first 4KiB NOR to be read, we must finish doing what we know of
|
||
|
|
* the NOR mux in this space in order to continue.
|
||
|
|
*/
|
||
|
|
#ifdef CONFIG_NOR_BOOT
|
||
|
|
enable_norboot_pin_mux();
|
||
|
|
#endif
|
||
|
|
watchdog_disable();
|
||
|
|
set_uart_mux_conf();
|
||
|
|
setup_early_clocks();
|
||
|
|
uart_soft_reset();
|
||
|
|
#ifdef CONFIG_SPL_BUILD
|
||
|
|
/*
|
||
|
|
* Save the boot parameters passed from romcode.
|
||
|
|
* We cannot delay the saving further than this,
|
||
|
|
* to prevent overwrites.
|
||
|
|
*/
|
||
|
|
save_omap_boot_params();
|
||
|
|
#endif
|
||
|
|
#ifdef CONFIG_DEBUG_UART_OMAP
|
||
|
|
debug_uart_init();
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef CONFIG_SPL_BUILD
|
||
|
|
spl_early_init();
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef CONFIG_TI_I2C_BOARD_DETECT
|
||
|
|
do_board_detect();
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
|
||
|
|
/* Enable RTC32K clock */
|
||
|
|
rtc32k_enable();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_SPL_BUILD
|
||
|
|
void board_init_f(ulong dummy)
|
||
|
|
{
|
||
|
|
hw_data_init();
|
||
|
|
early_system_init();
|
||
|
|
board_early_init_f();
|
||
|
|
sdram_init();
|
||
|
|
/* dram_init must store complete ramsize in gd->ram_size */
|
||
|
|
gd->ram_size = get_ram_size(
|
||
|
|
(void *)CONFIG_SYS_SDRAM_BASE,
|
||
|
|
CONFIG_MAX_RAM_BANK_SIZE);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
int arch_cpu_init_dm(void)
|
||
|
|
{
|
||
|
|
hw_data_init();
|
||
|
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||
|
|
early_system_init();
|
||
|
|
#endif
|
||
|
|
return 0;
|
||
|
|
}
|