114 lines
2.0 KiB
C
114 lines
2.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 MediaTek Inc.
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* Copyright (C) 2019 BayLibre, SAS
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* Author: Fabien Parent <fparent@baylibre.com>
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <ram.h>
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#include <asm/arch/misc.h>
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#include <asm/armv8/mmu.h>
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#include <asm/sections.h>
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#include <dm/uclass.h>
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#include <dt-bindings/clock/mt8516-clk.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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int ret;
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ret = fdtdec_setup_memory_banksize();
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if (ret)
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return ret;
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return fdtdec_setup_mem_size_base();
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = gd->ram_base;
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gd->bd->bi_dram[0].size = gd->ram_size;
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return 0;
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}
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int mtk_pll_early_init(void)
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{
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unsigned long pll_rates[] = {
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[CLK_APMIXED_ARMPLL] = 1300000000,
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[CLK_APMIXED_MAINPLL] = 1501000000,
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[CLK_APMIXED_UNIVPLL] = 1248000000,
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[CLK_APMIXED_MMPLL] = 380000000,
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};
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struct udevice *dev;
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int ret, i;
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_GET_DRIVER(mtk_clk_apmixedsys), &dev);
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if (ret)
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return ret;
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/* configure default rate then enable apmixedsys */
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for (i = 0; i < ARRAY_SIZE(pll_rates); i++) {
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struct clk clk = { .id = i, .dev = dev };
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ret = clk_set_rate(&clk, pll_rates[i]);
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if (ret)
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return ret;
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ret = clk_enable(&clk);
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if (ret)
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return ret;
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}
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return 0;
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}
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int mtk_soc_early_init(void)
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{
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int ret;
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/* initialize early clocks */
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ret = mtk_pll_early_init();
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if (ret)
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return ret;
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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psci_system_reset();
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}
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int print_cpuinfo(void)
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{
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printf("CPU: MediaTek MT8516\n");
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return 0;
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}
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static struct mm_region mt8516_mem_map[] = {
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{
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/* DDR */
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0x20000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
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}, {
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.virt = 0x00000000UL,
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.phys = 0x00000000UL,
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.size = 0x20000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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0,
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}
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};
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struct mm_region *mem_map = mt8516_mem_map;
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