106 lines
2.1 KiB
C
106 lines
2.1 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2013 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/mach-imx/regs-common.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* 1 second delay should be plenty of time for block reset. */
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#define RESET_MAX_TIMEOUT 1000000
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#define MXS_BLOCK_SFTRST (1 << 31)
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#define MXS_BLOCK_CLKGATE (1 << 30)
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int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
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int timeout)
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{
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while (--timeout) {
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if ((readl(®->reg) & mask) == mask)
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break;
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udelay(1);
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}
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return !timeout;
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}
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int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
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int timeout)
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{
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while (--timeout) {
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if ((readl(®->reg) & mask) == 0)
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break;
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udelay(1);
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}
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return !timeout;
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}
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int mxs_reset_block(struct mxs_register_32 *reg)
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{
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/* Clear SFTRST */
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writel(MXS_BLOCK_SFTRST, ®->reg_clr);
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if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
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return 1;
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/* Clear CLKGATE */
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writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
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/* Set SFTRST */
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writel(MXS_BLOCK_SFTRST, ®->reg_set);
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/* Wait for CLKGATE being set */
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if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
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return 1;
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/* Clear SFTRST */
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writel(MXS_BLOCK_SFTRST, ®->reg_clr);
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if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
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return 1;
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/* Clear CLKGATE */
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writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
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if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
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return 1;
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return 0;
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}
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static ulong get_sp(void)
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{
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ulong ret;
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asm("mov %0, sp" : "=r"(ret) : );
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return ret;
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}
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void board_lmb_reserve(struct lmb *lmb)
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{
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ulong sp, bank_end;
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int bank;
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sp = get_sp();
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debug("## Current stack ends at 0x%08lx ", sp);
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/* adjust sp by 16K to be safe */
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sp -= 4096 << 2;
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for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
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if (sp < gd->bd->bi_dram[bank].start)
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continue;
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bank_end = gd->bd->bi_dram[bank].start +
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gd->bd->bi_dram[bank].size;
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if (sp >= bank_end)
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continue;
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lmb_reserve(lmb, sp, bank_end - sp);
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break;
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}
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}
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