343 lines
9.6 KiB
C
343 lines
9.6 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* ddrmc DDR3 calibration code for NXP's VF610
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*
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* Copyright (C) 2018 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*
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*/
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/* #define DEBUG */
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <linux/bitmap.h>
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#include "ddrmc-vf610-calibration.h"
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/*
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* Documents:
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*
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* [1] "Vybrid: About DDR leveling feature on DDRMC."
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* https://community.nxp.com/thread/395323
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*
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* [2] VFxxx Controller Reference Manual, Rev. 0, 10/2016
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*
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*
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* NOTE
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* ====
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*
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* NXP recommends setting 'fixed' parameters instead of performing the
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* training at each boot.
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*
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* Use those functions to determine those values on new HW, read the
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* calculated value from registers and add them to the board specific
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* struct ddrmc_cr_setting.
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*
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* SW leveling supported operations - CR93[SW_LVL_MODE]:
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*
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* - 0x0 (b'00) - No leveling
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*
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* - 0x1 (b'01) - WRLVL_DL_X - It is not recommended to perform this tuning
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* on HW designs utilizing non-flyback topology
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* (Single DDR3 with x16).
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* Instead the WRLVL_DL_0/1 fields shall be set
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* based on trace length differences from their
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* layout.
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* Mismatches up to 25% or tCK (clock period) are
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* allowed, so the value in the filed doesn’t have
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* to be very accurate.
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*
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* - 0x2 (b'10) - RDLVL_DL_0/1 - refers to adjusting the DQS strobe in relation
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* to the DQ signals so that the strobe edge is
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* centered in the window of valid read data.
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*
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* - 0x3 (b'11) - RDLVL_GTDL_0/1 - refers to the delay the PHY uses to un-gate
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* the Read DQS strobe pad from the time that the
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* PHY enables the pad to input the strobe signal.
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*
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*/
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static int ddr_cal_get_first_edge_index(unsigned long *bmap, enum edge e,
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int samples, int start, int max)
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{
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int i, ret = -1;
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/*
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* We look only for the first value (and filter out
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* some wrong data)
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*/
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switch (e) {
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case RISING_EDGE:
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for (i = start; i <= max - samples; i++) {
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if (test_bit(i, bmap)) {
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if (!test_bit(i - 1, bmap) &&
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test_bit(i + 1, bmap) &&
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test_bit(i + 2, bmap) &&
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test_bit(i + 3, bmap)) {
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return i;
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}
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}
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}
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break;
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case FALLING_EDGE:
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for (i = start; i <= max - samples; i++) {
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if (!test_bit(i, bmap)) {
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if (test_bit(i - 1, bmap) &&
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test_bit(i - 2, bmap) &&
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test_bit(i - 3, bmap)) {
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return i;
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}
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}
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}
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}
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return ret;
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}
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static void bitmap_print(unsigned long *bmap, int max)
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{
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int i;
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debug("BITMAP [0x%p]:\n", bmap);
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for (i = 0; i <= max; i++) {
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debug("%d ", test_bit(i, bmap) ? 1 : 0);
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if (i && (i % 32) == (32 - 1))
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debug("\n");
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}
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debug("\n");
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}
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#define sw_leveling_op_done \
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while (!(readl(&ddrmr->cr[94]) & DDRMC_CR94_SWLVL_OP_DONE))
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#define sw_leveling_load_value \
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do { clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SWLVL_LOAD, \
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DDRMC_CR93_SWLVL_LOAD); } while (0)
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#define sw_leveling_start \
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do { clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SWLVL_START, \
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DDRMC_CR93_SWLVL_START); } while (0)
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#define sw_leveling_exit \
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do { clrsetbits_le32(&ddrmr->cr[94], DDRMC_CR94_SWLVL_EXIT, \
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DDRMC_CR94_SWLVL_EXIT); } while (0)
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/*
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* RDLVL_DL calibration:
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*
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* NXP is _NOT_ recommending performing the leveling at each
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* boot. Instead - one shall run this procedure on new boards
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* and then use hardcoded values.
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*
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*/
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static int ddrmc_cal_dqs_to_dq(struct ddrmr_regs *ddrmr)
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{
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DECLARE_BITMAP(rdlvl_rsp, DDRMC_DQS_DQ_MAX_DELAY + 1);
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int rdlvl_dl_0_min = -1, rdlvl_dl_0_max = -1;
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int rdlvl_dl_1_min = -1, rdlvl_dl_1_max = -1;
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int rdlvl_dl_0, rdlvl_dl_1;
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u8 swlvl_rsp;
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u32 tmp;
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int i;
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/* Read defaults */
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u16 rdlvl_dl_0_def =
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(readl(&ddrmr->cr[105]) >> DDRMC_CR105_RDLVL_DL_0_OFF) & 0xFFFF;
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u16 rdlvl_dl_1_def = readl(&ddrmr->cr[110]) & 0xFFFF;
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debug("\nRDLVL: ======================\n");
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debug("RDLVL: DQS to DQ (RDLVL)\n");
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debug("RDLVL: RDLVL_DL_0_DFL:\t 0x%x\n", rdlvl_dl_0_def);
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debug("RDLVL: RDLVL_DL_1_DFL:\t 0x%x\n", rdlvl_dl_1_def);
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/*
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* Set/Read setup for calibration
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*
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* Values necessary for leveling from Vybrid RM [2] - page 1600
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*/
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writel(0x40703030, &ddrmr->cr[144]);
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writel(0x40, &ddrmr->cr[145]);
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writel(0x40, &ddrmr->cr[146]);
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tmp = readl(&ddrmr->cr[144]);
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debug("RDLVL: PHY_RDLVL_RES:\t 0x%x\n", (tmp >> 24) & 0xFF);// set 0x40
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debug("RDLVL: PHY_RDLV_LOAD:\t 0x%x\n", (tmp >> 16) & 0xFF);// set 0x70
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debug("RDLVL: PHY_RDLV_DLL:\t 0x%x\n", (tmp >> 8) & 0xFF); // set 0x30
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debug("RDLVL: PHY_RDLV_EN:\t 0x%x\n", tmp & 0xFF); //set 0x30
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tmp = readl(&ddrmr->cr[145]);
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debug("RDLVL: PHY_RDLV_RR:\t 0x%x\n", tmp & 0x3FF); //set 0x40
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tmp = readl(&ddrmr->cr[146]);
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debug("RDLVL: PHY_RDLV_RESP:\t 0x%x\n", tmp); //set 0x40
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/*
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* Program/read the leveling edge RDLVL_EDGE = 0
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*
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* 0x00 is the correct output on SWLVL_RSP_X
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* If by any chance 1s are visible -> wrong number read
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*/
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clrbits_le32(&ddrmr->cr[101], DDRMC_CR101_PHY_RDLVL_EDGE);
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tmp = readl(&ddrmr->cr[101]);
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debug("RDLVL: PHY_RDLVL_EDGE:\t 0x%x\n",
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(tmp >> DDRMC_CR101_PHY_RDLVL_EDGE_OFF) & 0x1); //set 0
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/* Program Leveling mode - CR93[SW_LVL_MODE] to ’b10 */
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clrsetbits_le32(&ddrmr->cr[93], DDRMC_CR93_SW_LVL_MODE(0x3),
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DDRMC_CR93_SW_LVL_MODE(0x2));
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tmp = readl(&ddrmr->cr[93]);
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debug("RDLVL: SW_LVL_MODE:\t 0x%x\n",
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(tmp >> DDRMC_CR93_SW_LVL_MODE_OFF) & 0x3);
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/* Start procedure - CR93[SWLVL_START] to ’b1 */
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sw_leveling_start;
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/* Poll CR94[SWLVL_OP_DONE] */
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sw_leveling_op_done;
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/*
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* Program delays for RDLVL_DL_0
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*
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* The procedure is to increase the delay values from 0 to 0xFF
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* and read the response from the DDRMC
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*/
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debug("\nRDLVL: ---> RDLVL_DL_0\n");
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bitmap_zero(rdlvl_rsp, DDRMC_DQS_DQ_MAX_DELAY + 1);
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for (i = 0; i <= DDRMC_DQS_DQ_MAX_DELAY; i++) {
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clrsetbits_le32(&ddrmr->cr[105],
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0xFFFF << DDRMC_CR105_RDLVL_DL_0_OFF,
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i << DDRMC_CR105_RDLVL_DL_0_OFF);
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/* Load values CR93[SWLVL_LOAD] to ’b1 */
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sw_leveling_load_value;
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/* Poll CR94[SWLVL_OP_DONE] */
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sw_leveling_op_done;
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/*
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* Read Responses - SWLVL_RESP_0
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*
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* The 0x00 (correct response when PHY_RDLVL_EDGE = 0)
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* -> 1 in the bit vector
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*/
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swlvl_rsp = (readl(&ddrmr->cr[94]) >>
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DDRMC_CR94_SWLVL_RESP_0_OFF) & 0xF;
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if (swlvl_rsp == 0)
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generic_set_bit(i, rdlvl_rsp);
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}
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bitmap_print(rdlvl_rsp, DDRMC_DQS_DQ_MAX_DELAY);
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/*
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* First test for rising edge 0x0 -> 0x1 in bitmap
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*/
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rdlvl_dl_0_min = ddr_cal_get_first_edge_index(rdlvl_rsp, RISING_EDGE,
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N_SAMPLES, N_SAMPLES,
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DDRMC_DQS_DQ_MAX_DELAY);
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/*
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* Secondly test for falling edge 0x1 -> 0x0 in bitmap
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*/
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rdlvl_dl_0_max = ddr_cal_get_first_edge_index(rdlvl_rsp, FALLING_EDGE,
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N_SAMPLES, rdlvl_dl_0_min,
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DDRMC_DQS_DQ_MAX_DELAY);
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debug("RDLVL: DL_0 min: %d [0x%x] DL_0 max: %d [0x%x]\n",
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rdlvl_dl_0_min, rdlvl_dl_0_min, rdlvl_dl_0_max, rdlvl_dl_0_max);
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rdlvl_dl_0 = (rdlvl_dl_0_max - rdlvl_dl_0_min) / 2;
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if (rdlvl_dl_0_max == -1 || rdlvl_dl_0_min == -1 || rdlvl_dl_0 <= 0) {
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debug("RDLVL: The DQS to DQ delay cannot be found!\n");
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debug("RDLVL: Using default - slice 0: %d!\n", rdlvl_dl_0_def);
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rdlvl_dl_0 = rdlvl_dl_0_def;
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}
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debug("\nRDLVL: ---> RDLVL_DL_1\n");
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bitmap_zero(rdlvl_rsp, DDRMC_DQS_DQ_MAX_DELAY + 1);
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for (i = 0; i <= DDRMC_DQS_DQ_MAX_DELAY; i++) {
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clrsetbits_le32(&ddrmr->cr[110],
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0xFFFF << DDRMC_CR110_RDLVL_DL_1_OFF,
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i << DDRMC_CR110_RDLVL_DL_1_OFF);
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/* Load values CR93[SWLVL_LOAD] to ’b1 */
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sw_leveling_load_value;
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/* Poll CR94[SWLVL_OP_DONE] */
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sw_leveling_op_done;
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/*
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* Read Responses - SWLVL_RESP_1
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*
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* The 0x00 (correct response when PHY_RDLVL_EDGE = 0)
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* -> 1 in the bit vector
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*/
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swlvl_rsp = (readl(&ddrmr->cr[95]) >>
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DDRMC_CR95_SWLVL_RESP_1_OFF) & 0xF;
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if (swlvl_rsp == 0)
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generic_set_bit(i, rdlvl_rsp);
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}
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bitmap_print(rdlvl_rsp, DDRMC_DQS_DQ_MAX_DELAY);
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/*
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* First test for rising edge 0x0 -> 0x1 in bitmap
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*/
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rdlvl_dl_1_min = ddr_cal_get_first_edge_index(rdlvl_rsp, RISING_EDGE,
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N_SAMPLES, N_SAMPLES,
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DDRMC_DQS_DQ_MAX_DELAY);
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/*
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* Secondly test for falling edge 0x1 -> 0x0 in bitmap
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*/
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rdlvl_dl_1_max = ddr_cal_get_first_edge_index(rdlvl_rsp, FALLING_EDGE,
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N_SAMPLES, rdlvl_dl_1_min,
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DDRMC_DQS_DQ_MAX_DELAY);
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debug("RDLVL: DL_1 min: %d [0x%x] DL_1 max: %d [0x%x]\n",
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rdlvl_dl_1_min, rdlvl_dl_1_min, rdlvl_dl_1_max, rdlvl_dl_1_max);
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rdlvl_dl_1 = (rdlvl_dl_1_max - rdlvl_dl_1_min) / 2;
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if (rdlvl_dl_1_max == -1 || rdlvl_dl_1_min == -1 || rdlvl_dl_1 <= 0) {
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debug("RDLVL: The DQS to DQ delay cannot be found!\n");
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debug("RDLVL: Using default - slice 1: %d!\n", rdlvl_dl_1_def);
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rdlvl_dl_1 = rdlvl_dl_1_def;
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}
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debug("RDLVL: CALIBRATED: rdlvl_dl_0: 0x%x\t rdlvl_dl_1: 0x%x\n",
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rdlvl_dl_0, rdlvl_dl_1);
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/* Write new delay values */
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writel(DDRMC_CR105_RDLVL_DL_0(rdlvl_dl_0), &ddrmr->cr[105]);
|
|||
|
|
writel(DDRMC_CR110_RDLVL_DL_1(rdlvl_dl_1), &ddrmr->cr[110]);
|
|||
|
|
|
|||
|
|
sw_leveling_load_value;
|
|||
|
|
sw_leveling_op_done;
|
|||
|
|
|
|||
|
|
/* Exit procedure - CR94[SWLVL_EXIT] to ’b1 */
|
|||
|
|
sw_leveling_exit;
|
|||
|
|
|
|||
|
|
/* Poll CR94[SWLVL_OP_DONE] */
|
|||
|
|
sw_leveling_op_done;
|
|||
|
|
|
|||
|
|
return 0;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/*
|
|||
|
|
* WRLVL_DL calibration:
|
|||
|
|
*
|
|||
|
|
* For non-flyback memory architecture - where one have a single DDR3 x16
|
|||
|
|
* memory - it is NOT necessary to perform "Write Leveling"
|
|||
|
|
* [3] 'Vybrid DDR3 write leveling' https://community.nxp.com/thread/429362
|
|||
|
|
*
|
|||
|
|
*/
|
|||
|
|
|
|||
|
|
int ddrmc_calibration(struct ddrmr_regs *ddrmr)
|
|||
|
|
{
|
|||
|
|
ddrmc_cal_dqs_to_dq(ddrmr);
|
|||
|
|
|
|||
|
|
return 0;
|
|||
|
|
}
|