393 lines
6.8 KiB
C
393 lines
6.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
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*/
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/* Tegra114 clock PLL tables */
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#ifndef _TEGRA114_CLOCK_TABLES_H_
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#define _TEGRA114_CLOCK_TABLES_H_
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/* The PLLs supported by the hardware */
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enum clock_id {
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CLOCK_ID_FIRST,
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CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
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CLOCK_ID_MEMORY,
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CLOCK_ID_PERIPH,
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CLOCK_ID_AUDIO,
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CLOCK_ID_USB,
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CLOCK_ID_DISPLAY,
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/* now the simple ones */
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CLOCK_ID_FIRST_SIMPLE,
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CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
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CLOCK_ID_EPCI,
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CLOCK_ID_SFROM32KHZ,
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/* These are the base clocks (inputs to the Tegra SOC) */
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CLOCK_ID_32KHZ,
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CLOCK_ID_OSC,
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CLOCK_ID_CLK_M,
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CLOCK_ID_COUNT, /* number of PLLs */
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CLOCK_ID_DISPLAY2, /* placeholder */
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CLOCK_ID_NONE = -1,
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};
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/* The clocks supported by the hardware */
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enum periph_id {
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PERIPH_ID_FIRST,
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/* Low word: 31:0 (DEVICES_L) */
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PERIPH_ID_CPU = PERIPH_ID_FIRST,
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PERIPH_ID_COP,
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PERIPH_ID_TRIGSYS,
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PERIPH_ID_RESERVED3,
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PERIPH_ID_RTC,
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PERIPH_ID_TMR,
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PERIPH_ID_UART1,
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PERIPH_ID_UART2,
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/* 8 */
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PERIPH_ID_GPIO,
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PERIPH_ID_SDMMC2,
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PERIPH_ID_SPDIF,
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PERIPH_ID_I2S1,
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PERIPH_ID_I2C1,
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PERIPH_ID_NDFLASH,
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PERIPH_ID_SDMMC1,
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PERIPH_ID_SDMMC4,
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/* 16 */
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PERIPH_ID_RESERVED16,
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PERIPH_ID_PWM,
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PERIPH_ID_I2S2,
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PERIPH_ID_EPP,
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PERIPH_ID_VI,
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PERIPH_ID_2D,
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PERIPH_ID_USBD,
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PERIPH_ID_ISP,
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/* 24 */
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PERIPH_ID_3D,
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PERIPH_ID_RESERVED24,
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PERIPH_ID_DISP2,
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PERIPH_ID_DISP1,
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PERIPH_ID_HOST1X,
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PERIPH_ID_VCP,
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PERIPH_ID_I2S0,
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PERIPH_ID_CACHE2,
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/* Middle word: 63:32 (DEVICES_H) */
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PERIPH_ID_MEM,
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PERIPH_ID_AHBDMA,
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PERIPH_ID_APBDMA,
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PERIPH_ID_RESERVED35,
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PERIPH_ID_KBC,
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PERIPH_ID_STAT_MON,
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PERIPH_ID_PMC,
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PERIPH_ID_FUSE,
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/* 40 */
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PERIPH_ID_KFUSE,
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PERIPH_ID_SBC1,
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PERIPH_ID_SNOR,
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PERIPH_ID_RESERVED43,
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PERIPH_ID_SBC2,
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PERIPH_ID_RESERVED45,
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PERIPH_ID_SBC3,
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PERIPH_ID_I2C5,
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/* 48 */
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PERIPH_ID_DSI,
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PERIPH_ID_TVO,
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PERIPH_ID_MIPI,
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PERIPH_ID_HDMI,
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PERIPH_ID_CSI,
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PERIPH_ID_TVDAC,
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PERIPH_ID_I2C2,
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PERIPH_ID_UART3,
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/* 56 */
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PERIPH_ID_RESERVED56,
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PERIPH_ID_EMC,
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PERIPH_ID_USB2,
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PERIPH_ID_USB3,
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PERIPH_ID_MPE,
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PERIPH_ID_VDE,
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PERIPH_ID_BSEA,
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PERIPH_ID_BSEV,
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/* Upper word 95:64 (DEVICES_U) */
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PERIPH_ID_SPEEDO,
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PERIPH_ID_UART4,
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PERIPH_ID_UART5,
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PERIPH_ID_I2C3,
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PERIPH_ID_SBC4,
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PERIPH_ID_SDMMC3,
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PERIPH_ID_PCIE,
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PERIPH_ID_OWR,
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/* 72 */
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PERIPH_ID_AFI,
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PERIPH_ID_CORESIGHT,
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PERIPH_ID_PCIEXCLK,
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PERIPH_ID_AVPUCQ,
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PERIPH_ID_RESERVED76,
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PERIPH_ID_RESERVED77,
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PERIPH_ID_RESERVED78,
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PERIPH_ID_DTV,
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/* 80 */
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PERIPH_ID_NANDSPEED,
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PERIPH_ID_I2CSLOW,
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PERIPH_ID_DSIB,
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PERIPH_ID_RESERVED83,
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PERIPH_ID_IRAMA,
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PERIPH_ID_IRAMB,
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PERIPH_ID_IRAMC,
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PERIPH_ID_IRAMD,
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/* 88 */
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PERIPH_ID_CRAM2,
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PERIPH_ID_RESERVED89,
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PERIPH_ID_MDOUBLER,
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PERIPH_ID_RESERVED91,
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PERIPH_ID_SUSOUT,
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PERIPH_ID_RESERVED93,
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PERIPH_ID_RESERVED94,
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PERIPH_ID_RESERVED95,
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PERIPH_ID_VW_FIRST,
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/* V word: 31:0 */
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PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
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PERIPH_ID_CPULP,
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PERIPH_ID_3D2,
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PERIPH_ID_MSELECT,
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PERIPH_ID_TSENSOR,
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PERIPH_ID_I2S3,
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PERIPH_ID_I2S4,
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PERIPH_ID_I2C4,
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/* 104 */
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PERIPH_ID_SBC5,
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PERIPH_ID_SBC6,
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PERIPH_ID_AUDIO,
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PERIPH_ID_APBIF,
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PERIPH_ID_DAM0,
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PERIPH_ID_DAM1,
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PERIPH_ID_DAM2,
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PERIPH_ID_HDA2CODEC2X,
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/* 112 */
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PERIPH_ID_ATOMICS,
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PERIPH_ID_EX_RESERVED17,
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PERIPH_ID_EX_RESERVED18,
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PERIPH_ID_EX_RESERVED19,
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PERIPH_ID_EX_RESERVED20,
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PERIPH_ID_EX_RESERVED21,
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PERIPH_ID_EX_RESERVED22,
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PERIPH_ID_ACTMON,
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/* 120 */
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PERIPH_ID_EX_RESERVED24,
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PERIPH_ID_EX_RESERVED25,
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PERIPH_ID_EX_RESERVED26,
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PERIPH_ID_EX_RESERVED27,
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PERIPH_ID_SATA,
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PERIPH_ID_HDA,
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PERIPH_ID_EX_RESERVED30,
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PERIPH_ID_EX_RESERVED31,
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/* W word: 31:0 */
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PERIPH_ID_HDA2HDMICODEC,
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PERIPH_ID_RESERVED1_SATACOLD,
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PERIPH_ID_RESERVED2_PCIERX0,
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PERIPH_ID_RESERVED3_PCIERX1,
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PERIPH_ID_RESERVED4_PCIERX2,
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PERIPH_ID_RESERVED5_PCIERX3,
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PERIPH_ID_RESERVED6_PCIERX4,
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PERIPH_ID_RESERVED7_PCIERX5,
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/* 136 */
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PERIPH_ID_CEC,
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PERIPH_ID_PCIE2_IOBIST,
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PERIPH_ID_EMC_IOBIST,
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PERIPH_ID_HDMI_IOBIST,
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PERIPH_ID_SATA_IOBIST,
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PERIPH_ID_MIPI_IOBIST,
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PERIPH_ID_EMC1_IOBIST,
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PERIPH_ID_XUSB,
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/* 144 */
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PERIPH_ID_CILAB,
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PERIPH_ID_CILCD,
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PERIPH_ID_CILE,
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PERIPH_ID_DSIA_LP,
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PERIPH_ID_DSIB_LP,
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PERIPH_ID_RESERVED21_ENTROPY,
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PERIPH_ID_RESERVED22_W,
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PERIPH_ID_RESERVED23_W,
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/* 152 */
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PERIPH_ID_RESERVED24_W,
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PERIPH_ID_AMX0,
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PERIPH_ID_ADX0,
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PERIPH_ID_DVFS,
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PERIPH_ID_XUSB_SS,
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PERIPH_ID_EMC_DLL,
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PERIPH_ID_MC1,
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PERIPH_ID_EMC1,
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PERIPH_ID_COUNT,
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PERIPH_ID_NONE = -1,
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};
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enum pll_out_id {
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PLL_OUT1,
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PLL_OUT2,
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PLL_OUT3,
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PLL_OUT4
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};
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/*
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* Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
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* callers to use the PERIPH_ID for all access to peripheral clocks to avoid
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* confusion bewteen PERIPH_ID_... and PERIPHC_...
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*
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* We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
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* confusing.
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*/
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enum periphc_internal_id {
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/* 0x00 */
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PERIPHC_I2S1,
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PERIPHC_I2S2,
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PERIPHC_SPDIF_OUT,
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PERIPHC_SPDIF_IN,
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PERIPHC_PWM,
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PERIPHC_05h,
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PERIPHC_SBC2,
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PERIPHC_SBC3,
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/* 0x08 */
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PERIPHC_08h,
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PERIPHC_I2C1,
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PERIPHC_I2C5,
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PERIPHC_0bh,
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PERIPHC_0ch,
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PERIPHC_SBC1,
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PERIPHC_DISP1,
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PERIPHC_DISP2,
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/* 0x10 */
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PERIPHC_CVE,
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PERIPHC_11h,
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PERIPHC_VI,
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PERIPHC_13h,
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PERIPHC_SDMMC1,
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PERIPHC_SDMMC2,
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PERIPHC_G3D,
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PERIPHC_G2D,
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/* 0x18 */
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PERIPHC_NDFLASH,
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PERIPHC_SDMMC4,
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PERIPHC_VFIR,
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PERIPHC_EPP,
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PERIPHC_MPE,
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PERIPHC_MIPI,
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PERIPHC_UART1,
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PERIPHC_UART2,
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/* 0x20 */
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PERIPHC_HOST1X,
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PERIPHC_21h,
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PERIPHC_TVO,
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PERIPHC_HDMI,
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PERIPHC_24h,
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PERIPHC_TVDAC,
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PERIPHC_I2C2,
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PERIPHC_EMC,
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/* 0x28 */
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PERIPHC_UART3,
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PERIPHC_29h,
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PERIPHC_VI_SENSOR,
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PERIPHC_2bh,
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PERIPHC_2ch,
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PERIPHC_SBC4,
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PERIPHC_I2C3,
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PERIPHC_SDMMC3,
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/* 0x30 */
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PERIPHC_UART4,
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PERIPHC_UART5,
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PERIPHC_VDE,
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PERIPHC_OWR,
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PERIPHC_NOR,
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PERIPHC_CSITE,
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PERIPHC_I2S0,
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PERIPHC_37h,
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PERIPHC_VW_FIRST,
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/* 0x38 */
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PERIPHC_G3D2 = PERIPHC_VW_FIRST,
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PERIPHC_MSELECT,
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PERIPHC_TSENSOR,
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PERIPHC_I2S3,
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PERIPHC_I2S4,
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PERIPHC_I2C4,
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PERIPHC_SBC5,
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PERIPHC_SBC6,
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/* 0x40 */
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PERIPHC_AUDIO,
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PERIPHC_41h,
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PERIPHC_DAM0,
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PERIPHC_DAM1,
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PERIPHC_DAM2,
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PERIPHC_HDA2CODEC2X,
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PERIPHC_ACTMON,
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PERIPHC_EXTPERIPH1,
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/* 0x48 */
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PERIPHC_EXTPERIPH2,
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PERIPHC_EXTPERIPH3,
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PERIPHC_NANDSPEED,
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PERIPHC_I2CSLOW,
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PERIPHC_SYS,
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PERIPHC_SPEEDO,
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PERIPHC_4eh,
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PERIPHC_4fh,
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/* 0x50 */
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PERIPHC_50h,
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PERIPHC_51h,
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PERIPHC_52h,
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PERIPHC_53h,
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PERIPHC_SATAOOB,
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PERIPHC_SATA,
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PERIPHC_HDA,
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PERIPHC_COUNT,
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||
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PERIPHC_NONE = -1,
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||
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};
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||
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|
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||
|
|
/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
|
||
|
|
#define PERIPH_REG(id) \
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||
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|
(id < PERIPH_ID_VW_FIRST) ? \
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||
|
|
((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
|
||
|
|
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||
|
|
/* Mask value for a clock (within PERIPH_REG(id)) */
|
||
|
|
#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
|
||
|
|
|
||
|
|
/* return 1 if a PLL ID is in range */
|
||
|
|
#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
|
||
|
|
|
||
|
|
/* return 1 if a peripheral ID is in range */
|
||
|
|
#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
|
||
|
|
(id) < PERIPH_ID_COUNT)
|
||
|
|
|
||
|
|
#endif /* _TEGRA114_CLOCK_TABLES_H_ */
|