207 lines
6.9 KiB
C
207 lines
6.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* tegra_i2s.h - Definitions for Tegra124 I2S driver.
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* Note, some structures (ex, CIF) are different in Tegra114.
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*
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* NVIDIA Tegra I2S controller
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* Modified from dc tegra_regs.h
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*
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* Copyright 2018 Google LLC
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*
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* Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef _TEGRA_I2S_H_
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#define _TEGRA_I2S_H_
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struct i2s_ctlr {
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u32 ctrl; /* I2S_CTRL_0, 0x00 */
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u32 timing; /* I2S_TIMING_0, 0x04 */
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u32 offset; /* I2S_OFFSET_0, 0x08 */
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u32 ch_ctrl; /* I2S_CH_CTRL_0, 0x0C */
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u32 slot_ctrl; /* I2S_SLOT_CTRL_0, 0x10 */
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u32 cif_tx_ctrl; /* I2S_CIF_TX_CTRL_0, 0x14 */
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u32 cif_rx_ctrl; /* I2S_CIF_RX_CTRL_0, 0x18 */
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u32 flowctl; /* I2S_FLOWCTL_0, 0x1C */
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u32 tx_step; /* I2S_TX_STEP_0, 0x20 */
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u32 flow_status; /* I2S_FLOW_STATUS_0, 0x24 */
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u32 flow_total; /* I2S_FLOW_TOTAL_0, 0x28 */
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u32 flow_over; /* I2S_FLOW_OVER_0, 0x2C */
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u32 flow_under; /* I2S_FLOW_UNDER_0, 0x30 */
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u32 reserved[12]; /* RESERVED, 0x34 - 0x60 */
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u32 slot_ctrl2; /* I2S_SLOT_CTRL2_0, 0x64*/
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};
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enum {
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I2S_CTRL_XFER_EN_TX = 1 << 31,
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I2S_CTRL_XFER_EN_RX = 1 << 30,
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I2S_CTRL_CG_EN = 1 << 29,
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I2S_CTRL_SOFT_RESET = 1 << 28,
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I2S_CTRL_TX_FLOWCTL_EN = 1 << 27,
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I2S_CTRL_OBS_SEL_SHIFT = 24,
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I2S_CTRL_OBS_SEL_MASK = 7 << I2S_CTRL_OBS_SEL_SHIFT,
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I2S_FRAME_FORMAT_LRCK = 0,
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I2S_FRAME_FORMAT_FSYNC = 1,
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I2S_CTRL_FRAME_FORMAT_SHIFT = 12,
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I2S_CTRL_FRAME_FORMAT_MASK = 7 << I2S_CTRL_FRAME_FORMAT_SHIFT,
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I2S_CTRL_FRAME_FORMAT_LRCK = I2S_FRAME_FORMAT_LRCK <<
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I2S_CTRL_FRAME_FORMAT_SHIFT,
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I2S_CTRL_FRAME_FORMAT_FSYNC = I2S_FRAME_FORMAT_FSYNC <<
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I2S_CTRL_FRAME_FORMAT_SHIFT,
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I2S_CTRL_MASTER_ENABLE = 1 << 10,
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I2S_LRCK_LEFT_LOW = 0,
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I2S_LRCK_RIGHT_LOW = 1,
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I2S_CTRL_LRCK_SHIFT = 9,
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I2S_CTRL_LRCK_MASK = 1 << I2S_CTRL_LRCK_SHIFT,
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I2S_CTRL_LRCK_L_LOW = I2S_LRCK_LEFT_LOW << I2S_CTRL_LRCK_SHIFT,
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I2S_CTRL_LRCK_R_LOW = I2S_LRCK_RIGHT_LOW << I2S_CTRL_LRCK_SHIFT,
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I2S_CTRL_LPBK_ENABLE = 1 << 8,
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I2S_BIT_CODE_LINEAR = 0,
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I2S_BIT_CODE_ULAW = 1,
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I2S_BIT_CODE_ALAW = 2,
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I2S_CTRL_BIT_CODE_SHIFT = 4,
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I2S_CTRL_BIT_CODE_MASK = 3 << I2S_CTRL_BIT_CODE_SHIFT,
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I2S_CTRL_BIT_CODE_LINEAR = I2S_BIT_CODE_LINEAR <<
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I2S_CTRL_BIT_CODE_SHIFT,
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I2S_CTRL_BIT_CODE_ULAW = I2S_BIT_CODE_ULAW << I2S_CTRL_BIT_CODE_SHIFT,
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I2S_CTRL_BIT_CODE_ALAW = I2S_BIT_CODE_ALAW << I2S_CTRL_BIT_CODE_SHIFT,
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I2S_BITS_8 = 1,
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I2S_BITS_12 = 2,
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I2S_BITS_16 = 3,
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I2S_BITS_20 = 4,
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I2S_BITS_24 = 5,
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I2S_BITS_28 = 6,
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I2S_BITS_32 = 7,
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/* Sample container size; see {RX,TX}_MASK field in CH_CTRL below */
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I2S_CTRL_BIT_SIZE_SHIFT = 0,
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I2S_CTRL_BIT_SIZE_MASK = 7 << I2S_CTRL_BIT_SIZE_SHIFT,
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I2S_CTRL_BIT_SIZE_8 = I2S_BITS_8 << I2S_CTRL_BIT_SIZE_SHIFT,
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I2S_CTRL_BIT_SIZE_12 = I2S_BITS_12 << I2S_CTRL_BIT_SIZE_SHIFT,
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I2S_CTRL_BIT_SIZE_16 = I2S_BITS_16 << I2S_CTRL_BIT_SIZE_SHIFT,
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I2S_CTRL_BIT_SIZE_20 = I2S_BITS_20 << I2S_CTRL_BIT_SIZE_SHIFT,
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I2S_CTRL_BIT_SIZE_24 = I2S_BITS_24 << I2S_CTRL_BIT_SIZE_SHIFT,
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I2S_CTRL_BIT_SIZE_28 = I2S_BITS_28 << I2S_CTRL_BIT_SIZE_SHIFT,
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I2S_CTRL_BIT_SIZE_32 = I2S_BITS_32 << I2S_CTRL_BIT_SIZE_SHIFT,
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I2S_TIMING_NON_SYM_ENABLE = 1 << 12,
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I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT = 0,
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I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US = 0x7ff,
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I2S_TIMING_CHANNEL_BIT_COUNT_MASK =
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I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US <<
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I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT,
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I2S_OFFSET_RX_DATA_OFFSET_SHIFT = 16,
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I2S_OFFSET_RX_DATA_OFFSET_MASK_US = 0x7ff,
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I2S_OFFSET_RX_DATA_OFFSET_MASK = I2S_OFFSET_RX_DATA_OFFSET_MASK_US <<
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I2S_OFFSET_RX_DATA_OFFSET_SHIFT,
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I2S_OFFSET_TX_DATA_OFFSET_SHIFT = 0,
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I2S_OFFSET_TX_DATA_OFFSET_MASK_US = 0x7ff,
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I2S_OFFSET_TX_DATA_OFFSET_MASK = I2S_OFFSET_TX_DATA_OFFSET_MASK_US <<
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I2S_OFFSET_TX_DATA_OFFSET_SHIFT,
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/* FSYNC width - 1 in bit clocks */
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I2S_CH_CTRL_FSYNC_WIDTH_SHIFT = 24,
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I2S_CH_CTRL_FSYNC_WIDTH_MASK_US = 0xff,
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I2S_CH_CTRL_FSYNC_WIDTH_MASK = I2S_CH_CTRL_FSYNC_WIDTH_MASK_US <<
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I2S_CH_CTRL_FSYNC_WIDTH_SHIFT,
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I2S_HIGHZ_NO = 0,
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I2S_HIGHZ_YES = 1,
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I2S_HIGHZ_ON_HALF_BIT_CLK = 2,
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I2S_CH_CTRL_HIGHZ_CTRL_SHIFT = 12,
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I2S_CH_CTRL_HIGHZ_CTRL_MASK = 3 << I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
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I2S_CH_CTRL_HIGHZ_CTRL_NO = I2S_HIGHZ_NO <<
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I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
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I2S_CH_CTRL_HIGHZ_CTRL_YES = I2S_HIGHZ_YES <<
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I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
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I2S_CH_CTRL_HIGHZ_CTRL_ON_HALF_BIT_CLK = I2S_HIGHZ_ON_HALF_BIT_CLK <<
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I2S_CH_CTRL_HIGHZ_CTRL_SHIFT,
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I2S_MSB_FIRST = 0,
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I2S_LSB_FIRST = 1,
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I2S_CH_CTRL_RX_BIT_ORDER_SHIFT = 10,
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I2S_CH_CTRL_RX_BIT_ORDER_MASK = 1 << I2S_CH_CTRL_RX_BIT_ORDER_SHIFT,
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I2S_CH_CTRL_RX_BIT_ORDER_MSB_FIRST = I2S_MSB_FIRST <<
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I2S_CH_CTRL_RX_BIT_ORDER_SHIFT,
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I2S_CH_CTRL_RX_BIT_ORDER_LSB_FIRST = I2S_LSB_FIRST <<
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I2S_CH_CTRL_RX_BIT_ORDER_SHIFT,
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I2S_CH_CTRL_TX_BIT_ORDER_SHIFT = 9,
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I2S_CH_CTRL_TX_BIT_ORDER_MASK = 1 << I2S_CH_CTRL_TX_BIT_ORDER_SHIFT,
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I2S_CH_CTRL_TX_BIT_ORDER_MSB_FIRST = I2S_MSB_FIRST <<
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I2S_CH_CTRL_TX_BIT_ORDER_SHIFT,
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I2S_CH_CTRL_TX_BIT_ORDER_LSB_FIRST = I2S_LSB_FIRST <<
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I2S_CH_CTRL_TX_BIT_ORDER_SHIFT,
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I2S_POS_EDGE = 0,
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I2S_NEG_EDGE = 1,
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I2S_CH_CTRL_EGDE_CTRL_SHIFT = 8,
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I2S_CH_CTRL_EGDE_CTRL_MASK = 1 << I2S_CH_CTRL_EGDE_CTRL_SHIFT,
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I2S_CH_CTRL_EGDE_CTRL_POS_EDGE = I2S_POS_EDGE <<
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I2S_CH_CTRL_EGDE_CTRL_SHIFT,
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I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE = I2S_NEG_EDGE <<
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I2S_CH_CTRL_EGDE_CTRL_SHIFT,
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/* Sample size is # bits from BIT_SIZE minus this field */
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I2S_CH_CTRL_RX_MASK_BITS_SHIFT = 4,
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I2S_CH_CTRL_RX_MASK_BITS_MASK_US = 7,
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I2S_CH_CTRL_RX_MASK_BITS_MASK = I2S_CH_CTRL_RX_MASK_BITS_MASK_US <<
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I2S_CH_CTRL_RX_MASK_BITS_SHIFT,
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I2S_CH_CTRL_TX_MASK_BITS_SHIFT = 0,
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I2S_CH_CTRL_TX_MASK_BITS_MASK_US = 7,
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I2S_CH_CTRL_TX_MASK_BITS_MASK = I2S_CH_CTRL_TX_MASK_BITS_MASK_US <<
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I2S_CH_CTRL_TX_MASK_BITS_SHIFT,
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/* Number of slots in frame, minus 1 */
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I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT = 16,
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I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US = 7,
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I2S_SLOT_CTRL_TOTAL_SLOTS_MASK = I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US <<
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I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT,
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/* TDM mode slot enable bitmask */
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I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT = 8,
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I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK =
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0xff << I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT,
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I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT = 0,
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I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK = 0xff <<
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I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT,
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I2S_FILTER_LINEAR = 0,
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I2S_FILTER_QUAD = 1,
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I2S_FLOWCTL_FILTER_SHIFT = 31,
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I2S_FLOWCTL_FILTER_MASK = 1 << I2S_FLOWCTL_FILTER_SHIFT,
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I2S_FLOWCTL_FILTER_LINEAR = I2S_FILTER_LINEAR <<
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I2S_FLOWCTL_FILTER_SHIFT,
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I2S_FLOWCTL_FILTER_QUAD = I2S_FILTER_QUAD << I2S_FLOWCTL_FILTER_SHIFT,
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I2S_TX_STEP_SHIFT = 0,
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I2S_TX_STEP_MASK_US = 0xffff,
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I2S_TX_STEP_MASK = I2S_TX_STEP_MASK_US << I2S_TX_STEP_SHIFT,
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I2S_FLOW_STATUS_UNDERFLOW = 1 << 31,
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I2S_FLOW_STATUS_OVERFLOW = 1 << 30,
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I2S_FLOW_STATUS_MONITOR_INT_EN = 1 << 4,
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I2S_FLOW_STATUS_COUNTER_CLR = 1 << 3,
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I2S_FLOW_STATUS_MONITOR_CLR = 1 << 2,
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I2S_FLOW_STATUS_COUNTER_EN = 1 << 1,
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I2S_FLOW_STATUS_MONITOR_EN = 1 << 0,
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};
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#endif /* _TEGRA_I2C_H_ */
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