52 lines
1.9 KiB
C
52 lines
1.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*/
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#ifndef __FSL_LS102XA_DEVDIS_H_
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#define __FSL_LS102XA_DEVDIS_H_
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#include <fsl_devdis.h>
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const struct devdis_table devdis_tbl[] = {
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{ "pbl", 0x0, 0x80000000 }, /* PBL */
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{ "esdhc", 0x0, 0x20000000 }, /* eSDHC */
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{ "qdma", 0x0, 0x800000 }, /* qDMA */
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{ "edma", 0x0, 0x400000 }, /* eDMA */
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{ "usb3", 0x0, 0x84000 }, /* USB3.0 controller and PHY*/
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{ "usb2", 0x0, 0x40000 }, /* USB2.0 controller */
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{ "sata", 0x0, 0x8000 }, /* SATA */
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{ "sec", 0x0, 0x200 }, /* SEC */
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{ "dcu", 0x0, 0x2 }, /* Display controller Unit */
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{ "qe", 0x0, 0x1 }, /* QUICC Engine */
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{ "etsec1", 0x1, 0x80000000 }, /* eTSEC1 controller */
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{ "etesc2", 0x1, 0x40000000 }, /* eTSEC2 controller */
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{ "etsec3", 0x1, 0x20000000 }, /* eTSEC3 controller */
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{ "pex1", 0x2, 0x80000000 }, /* PCIE controller 1 */
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{ "pex2", 0x2, 0x40000000 }, /* PCIE controller 2 */
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{ "duart1", 0x3, 0x20000000 }, /* DUART1 */
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{ "duart2", 0x3, 0x10000000 }, /* DUART2 */
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{ "qspi", 0x3, 0x8000000 }, /* QSPI */
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{ "ddr", 0x4, 0x80000000 }, /* DDR */
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{ "ocram1", 0x4, 0x8000000 }, /* OCRAM1 */
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{ "ifc", 0x4, 0x800000 }, /* IFC */
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{ "gpio", 0x4, 0x400000 }, /* GPIO */
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{ "dbg", 0x4, 0x200000 }, /* DBG */
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{ "can1", 0x4, 0x80000 }, /* FlexCAN1 */
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{ "can2_4", 0x4, 0x40000 }, /* FlexCAN2_3_4 */
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{ "ftm2_8", 0x4, 0x20000 }, /* FlexTimer2_3_4_5_6_7_8 */
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{ "secmon", 0x4, 0x4000 }, /* Security Monitor */
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{ "wdog1_2", 0x4, 0x400 }, /* WatchDog1_2 */
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{ "i2c2_3", 0x4, 0x200 }, /* I2C2_3 */
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{ "sai1_4", 0x4, 0x100 }, /* SAI1_2_3_4 */
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{ "lpuart2_6", 0x4, 0x80 }, /* LPUART2_3_4_5_6 */
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{ "dspi1_2", 0x4, 0x40 }, /* DSPI1_2 */
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{ "asrc", 0x4, 0x20 }, /* ASRC */
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{ "spdif", 0x4, 0x10 }, /* SPDIF */
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{ "i2c1", 0x4, 0x4 }, /* I2C1 */
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{ "lpuart1", 0x4, 0x2 }, /* LPUART1 */
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{ "ftm1", 0x4, 0x1 }, /* FlexTimer1 */
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};
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#endif
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