49 lines
1.3 KiB
C
49 lines
1.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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*/
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#ifndef __ASM_ARCH_IMX8_REGS_H__
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#define __ASM_ARCH_IMX8_REGS_H__
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#define ARCH_MXC
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#define LPUART_BASE 0x5A060000
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#define GPT1_BASE_ADDR 0x5D140000
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#define SCU_LPUART_BASE 0x33220000
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#define GPIO1_BASE_ADDR 0x5D080000
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#define GPIO2_BASE_ADDR 0x5D090000
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#define GPIO3_BASE_ADDR 0x5D0A0000
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#define GPIO4_BASE_ADDR 0x5D0B0000
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#define GPIO5_BASE_ADDR 0x5D0C0000
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#define GPIO6_BASE_ADDR 0x5D0D0000
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#define GPIO7_BASE_ADDR 0x5D0E0000
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#define GPIO8_BASE_ADDR 0x5D0F0000
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#define LPI2C1_BASE_ADDR 0x5A800000
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#define LPI2C2_BASE_ADDR 0x5A810000
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#define LPI2C3_BASE_ADDR 0x5A820000
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#define LPI2C4_BASE_ADDR 0x5A830000
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#define LPI2C5_BASE_ADDR 0x5A840000
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#ifdef CONFIG_IMX8QXP
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#define LVDS0_PHYCTRL_BASE 0x56221000
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#define LVDS1_PHYCTRL_BASE 0x56241000
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#define MIPI0_SS_BASE 0x56220000
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#define MIPI1_SS_BASE 0x56240000
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#endif
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#define APBH_DMA_ARB_BASE_ADDR 0x5B810000
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#define APBH_DMA_ARB_END_ADDR 0x5B81FFFF
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#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
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#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
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#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
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#define PASS_OVER_INFO_ADDR 0x0010fe00
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#define USB_BASE_ADDR 0x5b0d0000
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#define USB_PHY0_BASE_ADDR 0x5b100000
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#endif /* __ASM_ARCH_IMX8_REGS_H__ */
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