87 lines
1.8 KiB
Plaintext
87 lines
1.8 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Xilinx CSE NOR board DTS
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*
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* Copyright (C) 2018 Xilinx, Inc.
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*/
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/dts-v1/;
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#include "zynq-7000.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Zynq CSE NOR Board";
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compatible = "xlnx,zynq-cse-nor", "xlnx,zynq-7000";
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aliases {
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serial0 = &dcc;
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};
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memory@fffc0000 {
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device_type = "memory";
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reg = <0xFFFC0000 0x40000>;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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dcc: dcc {
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compatible = "arm,dcc";
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status = "disabled";
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u-boot,dm-pre-reloc;
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};
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amba: amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges;
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intc: interrupt-controller@f8f01000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xF8F01000 0x1000>,
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<0xF8F00100 0x100>;
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};
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slcr: slcr@f8000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
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reg = <0xF8000000 0x1000>;
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ranges;
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clkc: clkc@100 {
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#clock-cells = <1>;
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compatible = "xlnx,ps7-clkc";
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clock-output-names = "armpll", "ddrpll",
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"iopll", "cpu_6or4x",
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"cpu_3or2x", "cpu_2x", "cpu_1x",
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"ddr2x", "ddr3x", "dci",
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"lqspi", "smc", "pcap", "gem0",
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"gem1", "fclk0", "fclk1",
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"fclk2", "fclk3", "can0",
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"can1", "sdio0", "sdio1",
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"uart0", "uart1", "spi0",
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"spi1", "dma", "usb0_aper",
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"usb1_aper", "gem0_aper",
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"gem1_aper", "sdio0_aper",
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"sdio1_aper", "spi0_aper",
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"spi1_aper", "can0_aper",
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"can1_aper", "i2c0_aper",
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"i2c1_aper", "uart0_aper",
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"uart1_aper", "gpio_aper",
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"lqspi_aper", "smc_aper",
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"swdt", "dbg_trc", "dbg_apb";
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reg = <0x100 0x100>;
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};
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};
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};
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};
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&dcc {
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status = "okay";
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};
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