uboot/u-boot-stm32mp-2020.01/arch/arm/dts/meson-g12b.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2019 BayLibre, SAS
 * Author: Neil Armstrong <narmstrong@baylibre.com>
 */

#include "meson-g12-common.dtsi"
#include <dt-bindings/power/meson-g12a-power.h>

/ {
	compatible = "amlogic,g12b";

	cpus {
		#address-cells = <0x2>;
		#size-cells = <0x0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu100>;
				};

				core1 {
					cpu = <&cpu101>;
				};

				core2 {
					cpu = <&cpu102>;
				};

				core3 {
					cpu = <&cpu103>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x1>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		cpu100: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		cpu101: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x0 0x101>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		cpu102: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x0 0x102>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		cpu103: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x0 0x103>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		l2: l2-cache0 {
			compatible = "cache";
		};
	};
};

&clkc {
	compatible = "amlogic,g12b-clkc";
};

&ethmac {
	power-domains = <&pwrc PWRC_G12A_ETH_ID>;
};

&vpu {
	power-domains = <&pwrc PWRC_G12A_VPU_ID>;
};

&sd_emmc_a {
	amlogic,dram-access-quirk;
};