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<a name="S12Z-Addressing-Modes"></a>
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Next: <a rel="next" accesskey="n" href="S12Z-Register-Notation.html#S12Z-Register-Notation">S12Z Register Notation</a>,
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Previous: <a rel="previous" accesskey="p" href="S12Z-Syntax-Overview.html#S12Z-Syntax-Overview">S12Z Syntax Overview</a>,
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<h5 class="subsubsection">9.24.2.2 Addressing Modes</h5>
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<p><a name="index-S12Z-addressing-modes-1528"></a><a name="index-addressing-modes_002c-S12Z-1529"></a>
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The following addressing modes are understood for the S12Z.
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<dl>
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<dt><dfn>Immediate</dfn><dd>‘<samp><span class="samp">#</span><var>number</var></samp>’
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<br><dt><dfn>Immediate Bit Field</dfn><dd>‘<samp><span class="samp">#</span><var>width</var><span class="samp">:</span><var>offset</var></samp>’
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<p>Bit field instructions in the immediate mode require the width and offset to
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be specified.
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The <var>width</var> parameter specifies the number of bits in the field.
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It should be a number in the range [1,32].
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<var>Offset</var> determines the position within the field where the operation
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should start.
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It should be a number in the range [0,31].
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<br><dt><dfn>Relative</dfn><dd>‘<samp><span class="samp">*</span><var>symbol</var></samp>’, or ‘<samp><span class="samp">*[+-]</span><var>digits</var></samp>’
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<p>Program counter relative addresses have a width of 15 bits.
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Thus, they must be within the range [-32768, 32767].
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<br><dt><dfn>Register</dfn><dd>‘<samp><var>reg</var></samp>’
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<p><a name="index-register-names_002c-S12Z-1530"></a>Some instructions accept a register as an operand.
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In general, <var>reg</var> may be a
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data register (‘<samp><span class="samp">D0</span></samp>’, ‘<samp><span class="samp">D1</span></samp>’ <small class="dots">...</small> ‘<samp><span class="samp">D7</span></samp>’),
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the ‘<samp><span class="samp">X</span></samp>’ register or the ‘<samp><span class="samp">Y</span></samp>’ register.
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<p>A few instructions accept as an argument the stack pointer
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register (‘<samp><span class="samp">S</span></samp>’), and/or the program counter (‘<samp><span class="samp">P</span></samp>’).
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<p>Some very special instructions accept arguments which refer to the
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condition code register. For these arguments the syntax is
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‘<samp><span class="samp">CCR</span></samp>’, ‘<samp><span class="samp">CCH</span></samp>’ or ‘<samp><span class="samp">CCL</span></samp>’ which refer to the complete
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condition code register, the condition code register high byte
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and the condition code register low byte respectively.
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<br><dt><dfn>Absolute Direct</dfn><dd>‘<samp><var>symbol</var></samp>’, or ‘<samp><var>digits</var></samp>’
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<br><dt><dfn>Absolute Indirect</dfn><dd>‘<samp><span class="samp">[</span><var>symbol</var></samp>’, or ‘<samp><var>digits</var><span class="samp">]</span></samp>’
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<br><dt><dfn>Constant Offset Indexed</dfn><dd>‘<samp><span class="samp">(</span><var>number</var><span class="samp">,</span><var>reg</var><span class="samp">)</span></samp>’
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<p><var>Reg</var> may be either ‘<samp><span class="samp">X</span></samp>’, ‘<samp><span class="samp">Y</span></samp>’, ‘<samp><span class="samp">S</span></samp>’ or
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‘<samp><span class="samp">P</span></samp>’ or one of the data registers ‘<samp><span class="samp">D0</span></samp>’, ‘<samp><span class="samp">D1</span></samp>’ <small class="dots">...</small>
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‘<samp><span class="samp">D7</span></samp>’.
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If any of the registers ‘<samp><span class="samp">D2</span></samp>’ <small class="dots">...</small> ‘<samp><span class="samp">D5</span></samp>’ are specified, then the
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register value is treated as a signed value.
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Otherwise it is treated as unsigned.
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<var>Number</var> may be any integer in the range [-8388608,8388607].
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<br><dt><dfn>Offset Indexed Indirect</dfn><dd>‘<samp><span class="samp">[</span><var>number</var><span class="samp">,</span><var>reg</var><span class="samp">]</span></samp>’
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<p><var>Reg</var> may be either ‘<samp><span class="samp">X</span></samp>’, ‘<samp><span class="samp">Y</span></samp>’, ‘<samp><span class="samp">S</span></samp>’ or
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‘<samp><span class="samp">P</span></samp>’.
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<var>Number</var> may be any integer in the range [-8388608,8388607].
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<br><dt><dfn>Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement</dfn><dd>‘<samp><span class="samp">-</span><var>reg</var></samp>’,
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‘<samp><span class="samp">+</span><var>reg</var></samp>’,
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‘<samp><var>reg</var><span class="samp">-</span></samp>’ or
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‘<samp><var>reg</var><span class="samp">+</span></samp>’
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<p>This addressing mode is typically used to access a value at an address,
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and simultaneously to increment/decrement the register pointing to that
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address.
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Thus <var>reg</var> may be any of the 24 bit registers ‘<samp><span class="samp">X</span></samp>’, ‘<samp><span class="samp">Y</span></samp>’, or
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‘<samp><span class="samp">S</span></samp>’.
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Pre-increment and post-decrement are not available for
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register ‘<samp><span class="samp">S</span></samp>’ (only post-increment and pre-decrement are available).
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<br><dt><dfn>Register Offset Direct</dfn><dd>‘<samp><span class="samp">(</span><var>data-reg</var><span class="samp">,</span><var>reg</var><span class="samp">)</span></samp>’
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<p><var>Reg</var> can be either ‘<samp><span class="samp">X</span></samp>’, ‘<samp><span class="samp">Y</span></samp>’, or ‘<samp><span class="samp">S</span></samp>’.
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<var>Data-reg</var>
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must be one of the data registers ‘<samp><span class="samp">D0</span></samp>’, ‘<samp><span class="samp">D1</span></samp>’ <small class="dots">...</small> ‘<samp><span class="samp">D7</span></samp>’.
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If any of the registers ‘<samp><span class="samp">D2</span></samp>’ <small class="dots">...</small> ‘<samp><span class="samp">D5</span></samp>’ are specified, then
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the register value is treated as a signed value.
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Otherwise it is treated as unsigned.
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<br><dt><dfn>Register Offset Indirect</dfn><dd>‘<samp><span class="samp">[</span><var>data-reg</var><span class="samp">,</span><var>reg</var><span class="samp">]</span></samp>’
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<p><var>Reg</var> can be either ‘<samp><span class="samp">X</span></samp>’ or ‘<samp><span class="samp">Y</span></samp>’.
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<var>Data-reg</var>
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must be one of the data registers ‘<samp><span class="samp">D0</span></samp>’, ‘<samp><span class="samp">D1</span></samp>’ <small class="dots">...</small> ‘<samp><span class="samp">D7</span></samp>’.
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If any of the registers ‘<samp><span class="samp">D2</span></samp>’ <small class="dots">...</small> ‘<samp><span class="samp">D5</span></samp>’ are specified, then
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the register value is treated as a signed value.
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Otherwise it is treated as unsigned.
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</dl>
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<p>For example:
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<pre class="smallexample"> trap #197 ;; Immediate mode
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bra *+49 ;; Relative mode
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bra .L0 ;; ditto
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jmp 0xFE0034 ;; Absolute direct mode
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jmp [0xFD0012] ;; Absolute indirect mode
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inc.b (4,x) ;; Constant offset indexed mode
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jsr (45, d0) ;; ditto
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dec.w [4,y] ;; Constant offset indexed indirect mode
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clr.p (-s) ;; Pre-decrement mode
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neg.l (d0, s) ;; Register offset direct mode
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com.b [d1, x] ;; Register offset indirect mode
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psh cch ;; Register mode
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</pre>
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