G.5.14 Sparc Features

The ‘org.gnu.gdb.sparc.cpu’ feature is required for sparc32/sparc64 targets. It should describe the following registers:

• ‘g0’ through ‘g7’
• ‘o0’ through ‘o7’
• ‘l0’ through ‘l7’
• ‘i0’ through ‘i7’

They may be 32-bit or 64-bit depending on the target.

Also the ‘org.gnu.gdb.sparc.fpu’ feature is required for sparc32/sparc64 targets. It should describe the following registers:

• ‘f0’ through ‘f31’
• ‘f32’ through ‘f62’ for sparc64

The ‘org.gnu.gdb.sparc.cp0’ feature is required for sparc32/sparc64 targets. It should describe the following registers:

• ‘y’, ‘psr’, ‘wim’, ‘tbr’, ‘pc’, ‘npc’, ‘fsr’, and ‘csr’ for sparc32
• ‘pc’, ‘npc’, ‘state’, ‘fsr’, ‘fprs’, and ‘y’ for sparc64