9.16.4 i386-Mnemonics

9.16.4.1 Instruction Naming

Instruction mnemonics are suffixed with one character modifiers which specify the size of operands. The letters ‘b’, ‘w’, ‘l’ and ‘q’ specify byte, word, long and quadruple word operands. If no suffix is specified by an instruction then as tries to fill in the missing suffix based on the destination register operand (the last one by convention). Thus, ‘mov %ax, %bx’ is equivalent to ‘movw %ax, %bx’; also, ‘mov $1, %bx’ is equivalent to ‘movw $1, bx’. Note that this is incompatible with the AT&T Unix assembler which assumes that a missing mnemonic suffix implies long operand size. (This incompatibility does not affect compiler output since compilers always explicitly specify the mnemonic suffix.)

Almost all instructions have the same names in AT&T and Intel format. There are a few exceptions. The sign extend and zero extend instructions need two sizes to specify them. They need a size to sign/zero extend from and a size to zero extend to. This is accomplished by using two instruction mnemonic suffixes in AT&T syntax. Base names for sign extend and zero extend are ‘movs...’ and ‘movz...’ in AT&T syntax (‘movsx’ and ‘movzx’ in Intel syntax). The instruction mnemonic suffixes are tacked on to this base name, the from suffix before the to suffix. Thus, ‘movsbl %al, %edx’ is AT&T syntax for “move sign extend from %al to %edx.” Possible suffixes, thus, are ‘bl’ (from byte to long), ‘bw’ (from byte to word), ‘wl’ (from word to long), ‘bq’ (from byte to quadruple word), ‘wq’ (from word to quadruple word), and ‘lq’ (from long to quadruple word).

Different encoding options can be specified via pseudo prefixes:

• ‘{disp8}’ – prefer 8-bit displacement.
• ‘{disp32}’ – prefer 32-bit displacement.
• ‘{load}’ – prefer load-form instruction.
• ‘{store}’ – prefer store-form instruction.
• ‘{vex2}’ – prefer 2-byte VEX prefix for VEX instruction.
• ‘{vex3}’ – prefer 3-byte VEX prefix for VEX instruction.
• ‘{evex}’ – encode with EVEX prefix.
• ‘{rex}’ – prefer REX prefix for integer and legacy vector instructions (x86-64 only). Note that this differs from the ‘rex’ prefix which generates REX prefix unconditionally.
• ‘{nooptimize}’ – disable instruction size optimization.

The Intel-syntax conversion instructions

• ‘cbw’ — sign-extend byte in ‘%al’ to word in ‘%ax’,
• ‘cwde’ — sign-extend word in ‘%ax’ to long in ‘%eax’,
• ‘cwd’ — sign-extend word in ‘%ax’ to long in ‘%dx:%ax’,
• ‘cdq’ — sign-extend dword in ‘%eax’ to quad in ‘%edx:%eax’,
• ‘cdqe’ — sign-extend dword in ‘%eax’ to quad in ‘%rax’ (x86-64 only),
• ‘cqo’ — sign-extend quad in ‘%rax’ to octuple in ‘%rdx:%rax’ (x86-64 only),

are called ‘cbtw’, ‘cwtl’, ‘cwtd’, ‘cltd’, ‘cltq’, and ‘cqto’ in AT&T naming. as accepts either naming for these instructions.

Far call/jump instructions are ‘lcall’ and ‘ljmp’ in AT&T syntax, but are ‘call far’ and ‘jump far’ in Intel convention.

9.16.4.2 AT&T Mnemonic versus Intel Mnemonic

as supports assembly using Intel mnemonic. .intel_mnemonic selects Intel mnemonic with Intel syntax, and .att_mnemonic switches back to the usual AT&T mnemonic with AT&T syntax for compatibility with the output of gcc. Several x87 instructions, ‘fadd’, ‘fdiv’, ‘fdivp’, ‘fdivr’, ‘fdivrp’, ‘fmul’, ‘fsub’, ‘fsubp’, ‘fsubr’ and ‘fsubrp’, are implemented in AT&T System V/386 assembler with different mnemonics from those in Intel IA32 specification. gcc generates those instructions with AT&T mnemonic.