85 lines
5.0 KiB
HTML
85 lines
5.0 KiB
HTML
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<html lang="en">
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<head>
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<title>RISC-V Features - Debugging with GDB</title>
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<meta name="description" content="Debugging with GDB">
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="Standard-Target-Features.html#Standard-Target-Features" title="Standard Target Features">
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<link rel="prev" href="PowerPC-Features.html#PowerPC-Features" title="PowerPC Features">
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<link rel="next" href="S_002f390-and-System-z-Features.html#S_002f390-and-System-z-Features" title="S/390 and System z Features">
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<body>
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<div class="node">
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<a name="RISC-V-Features"></a>
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<a name="RISC_002dV-Features"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="S_002f390-and-System-z-Features.html#S_002f390-and-System-z-Features">S/390 and System z Features</a>,
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Previous: <a rel="previous" accesskey="p" href="PowerPC-Features.html#PowerPC-Features">PowerPC Features</a>,
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Up: <a rel="up" accesskey="u" href="Standard-Target-Features.html#Standard-Target-Features">Standard Target Features</a>
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<hr>
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</div>
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<h4 class="subsection">G.5.12 RISC-V Features</h4>
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<p><a name="index-target-descriptions_002c-RISC_002dV-Features-3669"></a>
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The ‘<samp><span class="samp">org.gnu.gdb.riscv.cpu</span></samp>’ feature is required for RISC-V
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targets. It should contain the registers ‘<samp><span class="samp">x0</span></samp>’ through
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‘<samp><span class="samp">x31</span></samp>’, and ‘<samp><span class="samp">pc</span></samp>’. Either the architectural names (‘<samp><span class="samp">x0</span></samp>’,
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‘<samp><span class="samp">x1</span></samp>’, etc) can be used, or the ABI names (‘<samp><span class="samp">zero</span></samp>’, ‘<samp><span class="samp">ra</span></samp>’,
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etc).
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<p>The ‘<samp><span class="samp">org.gnu.gdb.riscv.fpu</span></samp>’ feature is optional. If present, it
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should contain registers ‘<samp><span class="samp">f0</span></samp>’ through ‘<samp><span class="samp">f31</span></samp>’, ‘<samp><span class="samp">fflags</span></samp>’,
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‘<samp><span class="samp">frm</span></samp>’, and ‘<samp><span class="samp">fcsr</span></samp>’. As with the cpu feature, either the
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architectural register names, or the ABI names can be used.
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<p>The ‘<samp><span class="samp">org.gnu.gdb.riscv.virtual</span></samp>’ feature is optional. If present,
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it should contain registers that are not backed by real registers on
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the target, but are instead virtual, where the register value is
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derived from other target state. In many ways these are like
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<span class="sc">gdb</span>s pseudo-registers, except implemented by the target.
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Currently the only register expected in this set is the one byte
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‘<samp><span class="samp">priv</span></samp>’ register that contains the target's privilege level in the
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least significant two bits.
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<p>The ‘<samp><span class="samp">org.gnu.gdb.riscv.csr</span></samp>’ feature is optional. If present, it
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should contain all of the target's standard CSRs. Standard CSRs are
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those defined in the RISC-V specification documents. There is some
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overlap between this feature and the fpu feature; the ‘<samp><span class="samp">fflags</span></samp>’,
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‘<samp><span class="samp">frm</span></samp>’, and ‘<samp><span class="samp">fcsr</span></samp>’ registers could be in either feature. The
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expectation is that these registers will be in the fpu feature if the
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target has floating point hardware, but can be moved into the csr
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feature if the target has the floating point control registers, but no
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other floating point hardware.
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</body></html>
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