77 lines
3.2 KiB
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77 lines
3.2 KiB
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<title>OpenRISC 1000 - Debugging with GDB</title>
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<div class="node">
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<a name="OpenRISC-1000"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="PowerPC-Embedded.html#PowerPC-Embedded">PowerPC Embedded</a>,
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Previous: <a rel="previous" accesskey="p" href="MIPS-Embedded.html#MIPS-Embedded">MIPS Embedded</a>,
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Up: <a rel="up" accesskey="u" href="Embedded-Processors.html#Embedded-Processors">Embedded Processors</a>
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<hr>
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</div>
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<h4 class="subsection">21.3.6 OpenRISC 1000</h4>
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<p><a name="index-OpenRISC-1000-1587"></a>
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The OpenRISC 1000 provides a free RISC instruction set architecture. It is
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mainly provided as a soft-core which can run on Xilinx, Altera and other
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FPGA's.
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<p><span class="sc">gdb</span> for OpenRISC supports the below commands when connecting to
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a target:
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<a name="index-target-sim-1588"></a>
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<dl><dt><code>target sim</code><dd>
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Runs the builtin CPU simulator which can run very basic
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programs but does not support most hardware functions like MMU.
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For more complex use cases the user is advised to run an external
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target, and connect using ‘<samp><span class="samp">target remote</span></samp>’.
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<p>Example: <code>target sim</code>
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<br><dt><code>set debug or1k</code><dd>Toggle whether to display OpenRISC-specific debugging messages from the
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OpenRISC target support subsystem.
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<br><dt><code>show debug or1k</code><dd>Show whether OpenRISC-specific debugging messages are enabled.
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</dl>
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</body></html>
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