399 lines
22 KiB
HTML
399 lines
22 KiB
HTML
|
<html lang="en">
|
||
|
|
<head>
|
||
|
|
<title>i386-Options - Using as</title>
|
||
|
|
<meta http-equiv="Content-Type" content="text/html">
|
||
|
|
<meta name="description" content="Using as">
|
||
|
|
<meta name="generator" content="makeinfo 4.13">
|
||
|
|
<link title="Top" rel="start" href="index.html#Top">
|
||
|
|
<link rel="up" href="i386_002dDependent.html#i386_002dDependent" title="i386-Dependent">
|
||
|
|
<link rel="next" href="i386_002dDirectives.html#i386_002dDirectives" title="i386-Directives">
|
||
|
|
<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage">
|
||
|
|
<!--
|
||
|
|
This file documents the GNU Assembler "as".
|
||
|
|
|
||
|
|
Copyright (C) 1991-2019 Free Software Foundation, Inc.
|
||
|
|
|
||
|
|
Permission is granted to copy, distribute and/or modify this document
|
||
|
|
under the terms of the GNU Free Documentation License, Version 1.3
|
||
|
|
or any later version published by the Free Software Foundation;
|
||
|
|
with no Invariant Sections, with no Front-Cover Texts, and with no
|
||
|
|
Back-Cover Texts. A copy of the license is included in the
|
||
|
|
section entitled ``GNU Free Documentation License''.
|
||
|
|
|
||
|
|
-->
|
||
|
|
<meta http-equiv="Content-Style-Type" content="text/css">
|
||
|
|
<style type="text/css"><!--
|
||
|
|
pre.display { font-family:inherit }
|
||
|
|
pre.format { font-family:inherit }
|
||
|
|
pre.smalldisplay { font-family:inherit; font-size:smaller }
|
||
|
|
pre.smallformat { font-family:inherit; font-size:smaller }
|
||
|
|
pre.smallexample { font-size:smaller }
|
||
|
|
pre.smalllisp { font-size:smaller }
|
||
|
|
span.sc { font-variant:small-caps }
|
||
|
|
span.roman { font-family:serif; font-weight:normal; }
|
||
|
|
span.sansserif { font-family:sans-serif; font-weight:normal; }
|
||
|
|
--></style>
|
||
|
|
</head>
|
||
|
|
<body>
|
||
|
|
<div class="node">
|
||
|
|
<a name="i386-Options"></a>
|
||
|
|
<a name="i386_002dOptions"></a>
|
||
|
|
<p>
|
||
|
|
Next: <a rel="next" accesskey="n" href="i386_002dDirectives.html#i386_002dDirectives">i386-Directives</a>,
|
||
|
|
Up: <a rel="up" accesskey="u" href="i386_002dDependent.html#i386_002dDependent">i386-Dependent</a>
|
||
|
|
<hr>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<h4 class="subsection">9.16.1 Options</h4>
|
||
|
|
|
||
|
|
<p><a name="index-options-for-i386-1077"></a><a name="index-options-for-x86_002d64-1078"></a><a name="index-i386-options-1079"></a><a name="index-x86_002d64-options-1080"></a>
|
||
|
|
The i386 version of <code>as</code> has a few machine
|
||
|
|
dependent options:
|
||
|
|
|
||
|
|
<!-- man begin OPTIONS -->
|
||
|
|
|
||
|
|
<a name="index-g_t_0040samp_007b_002d_002d32_007d-option_002c-i386-1081"></a>
|
||
|
|
<a name="index-g_t_0040samp_007b_002d_002d32_007d-option_002c-x86_002d64-1082"></a>
|
||
|
|
<a name="index-g_t_0040samp_007b_002d_002dx32_007d-option_002c-i386-1083"></a>
|
||
|
|
<a name="index-g_t_0040samp_007b_002d_002dx32_007d-option_002c-x86_002d64-1084"></a>
|
||
|
|
<a name="index-g_t_0040samp_007b_002d_002d64_007d-option_002c-i386-1085"></a>
|
||
|
|
<a name="index-g_t_0040samp_007b_002d_002d64_007d-option_002c-x86_002d64-1086"></a>
|
||
|
|
<dl><dt><code>--32 | --x32 | --64</code><dd>Select the word size, either 32 bits or 64 bits. ‘<samp><span class="samp">--32</span></samp>’
|
||
|
|
implies Intel i386 architecture, while ‘<samp><span class="samp">--x32</span></samp>’ and ‘<samp><span class="samp">--64</span></samp>’
|
||
|
|
imply AMD x86-64 architecture with 32-bit or 64-bit word-size
|
||
|
|
respectively.
|
||
|
|
|
||
|
|
<p>These options are only available with the ELF object file format, and
|
||
|
|
require that the necessary BFD support has been included (on a 32-bit
|
||
|
|
platform you have to add –enable-64-bit-bfd to configure enable 64-bit
|
||
|
|
usage and use x86-64 as target platform).
|
||
|
|
|
||
|
|
<br><dt><code>-n</code><dd>By default, x86 GAS replaces multiple nop instructions used for
|
||
|
|
alignment within code sections with multi-byte nop instructions such
|
||
|
|
as leal 0(%esi,1),%esi. This switch disables the optimization if a single
|
||
|
|
byte nop (0x90) is explicitly specified as the fill byte for alignment.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002d_002ddivide_007d-option_002c-i386-1087"></a><br><dt><code>--divide</code><dd>On SVR4-derived platforms, the character ‘<samp><span class="samp">/</span></samp>’ is treated as a comment
|
||
|
|
character, which means that it cannot be used in expressions. The
|
||
|
|
‘<samp><span class="samp">--divide</span></samp>’ option turns ‘<samp><span class="samp">/</span></samp>’ into a normal character. This does
|
||
|
|
not disable ‘<samp><span class="samp">/</span></samp>’ at the beginning of a line starting a comment, or
|
||
|
|
affect using ‘<samp><span class="samp">#</span></samp>’ for starting a comment.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmarch_003d_007d-option_002c-i386-1088"></a><a name="index-g_t_0040samp_007b_002dmarch_003d_007d-option_002c-x86_002d64-1089"></a><br><dt><code>-march=</code><var>CPU</var><code>[+</code><var>EXTENSION</var><code>...]</code><dd>This option specifies the target processor. The assembler will
|
||
|
|
issue an error message if an attempt is made to assemble an instruction
|
||
|
|
which will not execute on the target processor. The following
|
||
|
|
processor names are recognized:
|
||
|
|
<code>i8086</code>,
|
||
|
|
<code>i186</code>,
|
||
|
|
<code>i286</code>,
|
||
|
|
<code>i386</code>,
|
||
|
|
<code>i486</code>,
|
||
|
|
<code>i586</code>,
|
||
|
|
<code>i686</code>,
|
||
|
|
<code>pentium</code>,
|
||
|
|
<code>pentiumpro</code>,
|
||
|
|
<code>pentiumii</code>,
|
||
|
|
<code>pentiumiii</code>,
|
||
|
|
<code>pentium4</code>,
|
||
|
|
<code>prescott</code>,
|
||
|
|
<code>nocona</code>,
|
||
|
|
<code>core</code>,
|
||
|
|
<code>core2</code>,
|
||
|
|
<code>corei7</code>,
|
||
|
|
<code>l1om</code>,
|
||
|
|
<code>k1om</code>,
|
||
|
|
<code>iamcu</code>,
|
||
|
|
<code>k6</code>,
|
||
|
|
<code>k6_2</code>,
|
||
|
|
<code>athlon</code>,
|
||
|
|
<code>opteron</code>,
|
||
|
|
<code>k8</code>,
|
||
|
|
<code>amdfam10</code>,
|
||
|
|
<code>bdver1</code>,
|
||
|
|
<code>bdver2</code>,
|
||
|
|
<code>bdver3</code>,
|
||
|
|
<code>bdver4</code>,
|
||
|
|
<code>znver1</code>,
|
||
|
|
<code>znver2</code>,
|
||
|
|
<code>btver1</code>,
|
||
|
|
<code>btver2</code>,
|
||
|
|
<code>generic32</code> and
|
||
|
|
<code>generic64</code>.
|
||
|
|
|
||
|
|
<p>In addition to the basic instruction set, the assembler can be told to
|
||
|
|
accept various extension mnemonics. For example,
|
||
|
|
<code>-march=i686+sse4+vmx</code> extends <var>i686</var> with <var>sse4</var> and
|
||
|
|
<var>vmx</var>. The following extensions are currently supported:
|
||
|
|
<code>8087</code>,
|
||
|
|
<code>287</code>,
|
||
|
|
<code>387</code>,
|
||
|
|
<code>687</code>,
|
||
|
|
<code>no87</code>,
|
||
|
|
<code>no287</code>,
|
||
|
|
<code>no387</code>,
|
||
|
|
<code>no687</code>,
|
||
|
|
<code>cmov</code>,
|
||
|
|
<code>nocmov</code>,
|
||
|
|
<code>fxsr</code>,
|
||
|
|
<code>nofxsr</code>,
|
||
|
|
<code>mmx</code>,
|
||
|
|
<code>nommx</code>,
|
||
|
|
<code>sse</code>,
|
||
|
|
<code>sse2</code>,
|
||
|
|
<code>sse3</code>,
|
||
|
|
<code>ssse3</code>,
|
||
|
|
<code>sse4.1</code>,
|
||
|
|
<code>sse4.2</code>,
|
||
|
|
<code>sse4</code>,
|
||
|
|
<code>nosse</code>,
|
||
|
|
<code>nosse2</code>,
|
||
|
|
<code>nosse3</code>,
|
||
|
|
<code>nossse3</code>,
|
||
|
|
<code>nosse4.1</code>,
|
||
|
|
<code>nosse4.2</code>,
|
||
|
|
<code>nosse4</code>,
|
||
|
|
<code>avx</code>,
|
||
|
|
<code>avx2</code>,
|
||
|
|
<code>noavx</code>,
|
||
|
|
<code>noavx2</code>,
|
||
|
|
<code>adx</code>,
|
||
|
|
<code>rdseed</code>,
|
||
|
|
<code>prfchw</code>,
|
||
|
|
<code>smap</code>,
|
||
|
|
<code>mpx</code>,
|
||
|
|
<code>sha</code>,
|
||
|
|
<code>rdpid</code>,
|
||
|
|
<code>ptwrite</code>,
|
||
|
|
<code>cet</code>,
|
||
|
|
<code>gfni</code>,
|
||
|
|
<code>vaes</code>,
|
||
|
|
<code>vpclmulqdq</code>,
|
||
|
|
<code>prefetchwt1</code>,
|
||
|
|
<code>clflushopt</code>,
|
||
|
|
<code>se1</code>,
|
||
|
|
<code>clwb</code>,
|
||
|
|
<code>movdiri</code>,
|
||
|
|
<code>movdir64b</code>,
|
||
|
|
<code>enqcmd</code>,
|
||
|
|
<code>avx512f</code>,
|
||
|
|
<code>avx512cd</code>,
|
||
|
|
<code>avx512er</code>,
|
||
|
|
<code>avx512pf</code>,
|
||
|
|
<code>avx512vl</code>,
|
||
|
|
<code>avx512bw</code>,
|
||
|
|
<code>avx512dq</code>,
|
||
|
|
<code>avx512ifma</code>,
|
||
|
|
<code>avx512vbmi</code>,
|
||
|
|
<code>avx512_4fmaps</code>,
|
||
|
|
<code>avx512_4vnniw</code>,
|
||
|
|
<code>avx512_vpopcntdq</code>,
|
||
|
|
<code>avx512_vbmi2</code>,
|
||
|
|
<code>avx512_vnni</code>,
|
||
|
|
<code>avx512_bitalg</code>,
|
||
|
|
<code>avx512_bf16</code>,
|
||
|
|
<code>noavx512f</code>,
|
||
|
|
<code>noavx512cd</code>,
|
||
|
|
<code>noavx512er</code>,
|
||
|
|
<code>noavx512pf</code>,
|
||
|
|
<code>noavx512vl</code>,
|
||
|
|
<code>noavx512bw</code>,
|
||
|
|
<code>noavx512dq</code>,
|
||
|
|
<code>noavx512ifma</code>,
|
||
|
|
<code>noavx512vbmi</code>,
|
||
|
|
<code>noavx512_4fmaps</code>,
|
||
|
|
<code>noavx512_4vnniw</code>,
|
||
|
|
<code>noavx512_vpopcntdq</code>,
|
||
|
|
<code>noavx512_vbmi2</code>,
|
||
|
|
<code>noavx512_vnni</code>,
|
||
|
|
<code>noavx512_bitalg</code>,
|
||
|
|
<code>noavx512_vp2intersect</code>,
|
||
|
|
<code>noavx512_bf16</code>,
|
||
|
|
<code>noenqcmd</code>,
|
||
|
|
<code>vmx</code>,
|
||
|
|
<code>vmfunc</code>,
|
||
|
|
<code>smx</code>,
|
||
|
|
<code>xsave</code>,
|
||
|
|
<code>xsaveopt</code>,
|
||
|
|
<code>xsavec</code>,
|
||
|
|
<code>xsaves</code>,
|
||
|
|
<code>aes</code>,
|
||
|
|
<code>pclmul</code>,
|
||
|
|
<code>fsgsbase</code>,
|
||
|
|
<code>rdrnd</code>,
|
||
|
|
<code>f16c</code>,
|
||
|
|
<code>bmi2</code>,
|
||
|
|
<code>fma</code>,
|
||
|
|
<code>movbe</code>,
|
||
|
|
<code>ept</code>,
|
||
|
|
<code>lzcnt</code>,
|
||
|
|
<code>hle</code>,
|
||
|
|
<code>rtm</code>,
|
||
|
|
<code>invpcid</code>,
|
||
|
|
<code>clflush</code>,
|
||
|
|
<code>mwaitx</code>,
|
||
|
|
<code>clzero</code>,
|
||
|
|
<code>wbnoinvd</code>,
|
||
|
|
<code>pconfig</code>,
|
||
|
|
<code>waitpkg</code>,
|
||
|
|
<code>cldemote</code>,
|
||
|
|
<code>lwp</code>,
|
||
|
|
<code>fma4</code>,
|
||
|
|
<code>xop</code>,
|
||
|
|
<code>cx16</code>,
|
||
|
|
<code>syscall</code>,
|
||
|
|
<code>rdtscp</code>,
|
||
|
|
<code>3dnow</code>,
|
||
|
|
<code>3dnowa</code>,
|
||
|
|
<code>sse4a</code>,
|
||
|
|
<code>sse5</code>,
|
||
|
|
<code>svme</code>,
|
||
|
|
<code>abm</code> and
|
||
|
|
<code>padlock</code>.
|
||
|
|
Note that rather than extending a basic instruction set, the extension
|
||
|
|
mnemonics starting with <code>no</code> revoke the respective functionality.
|
||
|
|
|
||
|
|
<p>When the <code>.arch</code> directive is used with <samp><span class="option">-march</span></samp>, the
|
||
|
|
<code>.arch</code> directive will take precedent.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmtune_003d_007d-option_002c-i386-1090"></a><a name="index-g_t_0040samp_007b_002dmtune_003d_007d-option_002c-x86_002d64-1091"></a><br><dt><code>-mtune=</code><var>CPU</var><dd>This option specifies a processor to optimize for. When used in
|
||
|
|
conjunction with the <samp><span class="option">-march</span></samp> option, only instructions
|
||
|
|
of the processor specified by the <samp><span class="option">-march</span></samp> option will be
|
||
|
|
generated.
|
||
|
|
|
||
|
|
<p>Valid <var>CPU</var> values are identical to the processor list of
|
||
|
|
<samp><span class="option">-march=</span><var>CPU</var></samp>.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmsse2avx_007d-option_002c-i386-1092"></a><a name="index-g_t_0040samp_007b_002dmsse2avx_007d-option_002c-x86_002d64-1093"></a><br><dt><code>-msse2avx</code><dd>This option specifies that the assembler should encode SSE instructions
|
||
|
|
with VEX prefix.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmsse_002dcheck_003d_007d-option_002c-i386-1094"></a><a name="index-g_t_0040samp_007b_002dmsse_002dcheck_003d_007d-option_002c-x86_002d64-1095"></a><br><dt><code>-msse-check=</code><var>none</var><dt><code>-msse-check=</code><var>warning</var><dt><code>-msse-check=</code><var>error</var><dd>These options control if the assembler should check SSE instructions.
|
||
|
|
<samp><span class="option">-msse-check=</span><var>none</var></samp> will make the assembler not to check SSE
|
||
|
|
instructions, which is the default. <samp><span class="option">-msse-check=</span><var>warning</var></samp>
|
||
|
|
will make the assembler issue a warning for any SSE instruction.
|
||
|
|
<samp><span class="option">-msse-check=</span><var>error</var></samp> will make the assembler issue an error
|
||
|
|
for any SSE instruction.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmavxscalar_003d_007d-option_002c-i386-1096"></a><a name="index-g_t_0040samp_007b_002dmavxscalar_003d_007d-option_002c-x86_002d64-1097"></a><br><dt><code>-mavxscalar=</code><var>128</var><dt><code>-mavxscalar=</code><var>256</var><dd>These options control how the assembler should encode scalar AVX
|
||
|
|
instructions. <samp><span class="option">-mavxscalar=</span><var>128</var></samp> will encode scalar
|
||
|
|
AVX instructions with 128bit vector length, which is the default.
|
||
|
|
<samp><span class="option">-mavxscalar=</span><var>256</var></samp> will encode scalar AVX instructions
|
||
|
|
with 256bit vector length.
|
||
|
|
|
||
|
|
<p>WARNING: Don't use this for production code - due to CPU errata the
|
||
|
|
resulting code may not work on certain models.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmvexwig_003d_007d-option_002c-i386-1098"></a><a name="index-g_t_0040samp_007b_002dmvexwig_003d_007d-option_002c-x86_002d64-1099"></a><br><dt><code>-mvexwig=</code><var>0</var><dt><code>-mvexwig=</code><var>1</var><dd>These options control how the assembler should encode VEX.W-ignored (WIG)
|
||
|
|
VEX instructions. <samp><span class="option">-mvexwig=</span><var>0</var></samp> will encode WIG VEX
|
||
|
|
instructions with vex.w = 0, which is the default.
|
||
|
|
<samp><span class="option">-mvexwig=</span><var>1</var></samp> will encode WIG EVEX instructions with
|
||
|
|
vex.w = 1.
|
||
|
|
|
||
|
|
<p>WARNING: Don't use this for production code - due to CPU errata the
|
||
|
|
resulting code may not work on certain models.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmevexlig_003d_007d-option_002c-i386-1100"></a><a name="index-g_t_0040samp_007b_002dmevexlig_003d_007d-option_002c-x86_002d64-1101"></a><br><dt><code>-mevexlig=</code><var>128</var><dt><code>-mevexlig=</code><var>256</var><dt><code>-mevexlig=</code><var>512</var><dd>These options control how the assembler should encode length-ignored
|
||
|
|
(LIG) EVEX instructions. <samp><span class="option">-mevexlig=</span><var>128</var></samp> will encode LIG
|
||
|
|
EVEX instructions with 128bit vector length, which is the default.
|
||
|
|
<samp><span class="option">-mevexlig=</span><var>256</var></samp> and <samp><span class="option">-mevexlig=</span><var>512</var></samp> will
|
||
|
|
encode LIG EVEX instructions with 256bit and 512bit vector length,
|
||
|
|
respectively.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmevexwig_003d_007d-option_002c-i386-1102"></a><a name="index-g_t_0040samp_007b_002dmevexwig_003d_007d-option_002c-x86_002d64-1103"></a><br><dt><code>-mevexwig=</code><var>0</var><dt><code>-mevexwig=</code><var>1</var><dd>These options control how the assembler should encode w-ignored (WIG)
|
||
|
|
EVEX instructions. <samp><span class="option">-mevexwig=</span><var>0</var></samp> will encode WIG
|
||
|
|
EVEX instructions with evex.w = 0, which is the default.
|
||
|
|
<samp><span class="option">-mevexwig=</span><var>1</var></samp> will encode WIG EVEX instructions with
|
||
|
|
evex.w = 1.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmmnemonic_003d_007d-option_002c-i386-1104"></a><a name="index-g_t_0040samp_007b_002dmmnemonic_003d_007d-option_002c-x86_002d64-1105"></a><br><dt><code>-mmnemonic=</code><var>att</var><dt><code>-mmnemonic=</code><var>intel</var><dd>This option specifies instruction mnemonic for matching instructions.
|
||
|
|
The <code>.att_mnemonic</code> and <code>.intel_mnemonic</code> directives will
|
||
|
|
take precedent.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmsyntax_003d_007d-option_002c-i386-1106"></a><a name="index-g_t_0040samp_007b_002dmsyntax_003d_007d-option_002c-x86_002d64-1107"></a><br><dt><code>-msyntax=</code><var>att</var><dt><code>-msyntax=</code><var>intel</var><dd>This option specifies instruction syntax when processing instructions.
|
||
|
|
The <code>.att_syntax</code> and <code>.intel_syntax</code> directives will
|
||
|
|
take precedent.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmnaked_002dreg_007d-option_002c-i386-1108"></a><a name="index-g_t_0040samp_007b_002dmnaked_002dreg_007d-option_002c-x86_002d64-1109"></a><br><dt><code>-mnaked-reg</code><dd>This option specifies that registers don't require a ‘<samp><span class="samp">%</span></samp>’ prefix.
|
||
|
|
The <code>.att_syntax</code> and <code>.intel_syntax</code> directives will take precedent.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmadd_002dbnd_002dprefix_007d-option_002c-i386-1110"></a><a name="index-g_t_0040samp_007b_002dmadd_002dbnd_002dprefix_007d-option_002c-x86_002d64-1111"></a><br><dt><code>-madd-bnd-prefix</code><dd>This option forces the assembler to add BND prefix to all branches, even
|
||
|
|
if such prefix was not explicitly specified in the source code.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmshared_007d-option_002c-i386-1112"></a><a name="index-g_t_0040samp_007b_002dmshared_007d-option_002c-x86_002d64-1113"></a><br><dt><code>-mno-shared</code><dd>On ELF target, the assembler normally optimizes out non-PLT relocations
|
||
|
|
against defined non-weak global branch targets with default visibility.
|
||
|
|
The ‘<samp><span class="samp">-mshared</span></samp>’ option tells the assembler to generate code which
|
||
|
|
may go into a shared library where all non-weak global branch targets
|
||
|
|
with default visibility can be preempted. The resulting code is
|
||
|
|
slightly bigger. This option only affects the handling of branch
|
||
|
|
instructions.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmbig_002dobj_007d-option_002c-x86_002d64-1114"></a><br><dt><code>-mbig-obj</code><dd>On x86-64 PE/COFF target this option forces the use of big object file
|
||
|
|
format, which allows more than 32768 sections.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmomit_002dlock_002dprefix_003d_007d-option_002c-i386-1115"></a><a name="index-g_t_0040samp_007b_002dmomit_002dlock_002dprefix_003d_007d-option_002c-x86_002d64-1116"></a><br><dt><code>-momit-lock-prefix=</code><var>no</var><dt><code>-momit-lock-prefix=</code><var>yes</var><dd>These options control how the assembler should encode lock prefix.
|
||
|
|
This option is intended as a workaround for processors, that fail on
|
||
|
|
lock prefix. This option can only be safely used with single-core,
|
||
|
|
single-thread computers
|
||
|
|
<samp><span class="option">-momit-lock-prefix=</span><var>yes</var></samp> will omit all lock prefixes.
|
||
|
|
<samp><span class="option">-momit-lock-prefix=</span><var>no</var></samp> will encode lock prefix as usual,
|
||
|
|
which is the default.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmfence_002das_002dlock_002dadd_003d_007d-option_002c-i386-1117"></a><a name="index-g_t_0040samp_007b_002dmfence_002das_002dlock_002dadd_003d_007d-option_002c-x86_002d64-1118"></a><br><dt><code>-mfence-as-lock-add=</code><var>no</var><dt><code>-mfence-as-lock-add=</code><var>yes</var><dd>These options control how the assembler should encode lfence, mfence and
|
||
|
|
sfence.
|
||
|
|
<samp><span class="option">-mfence-as-lock-add=</span><var>yes</var></samp> will encode lfence, mfence and
|
||
|
|
sfence as ‘<samp><span class="samp">lock addl $0x0, (%rsp)</span></samp>’ in 64-bit mode and
|
||
|
|
‘<samp><span class="samp">lock addl $0x0, (%esp)</span></samp>’ in 32-bit mode.
|
||
|
|
<samp><span class="option">-mfence-as-lock-add=</span><var>no</var></samp> will encode lfence, mfence and
|
||
|
|
sfence as usual, which is the default.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmrelax_002drelocations_003d_007d-option_002c-i386-1119"></a><a name="index-g_t_0040samp_007b_002dmrelax_002drelocations_003d_007d-option_002c-x86_002d64-1120"></a><br><dt><code>-mrelax-relocations=</code><var>no</var><dt><code>-mrelax-relocations=</code><var>yes</var><dd>These options control whether the assembler should generate relax
|
||
|
|
relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
|
||
|
|
R_X86_64_REX_GOTPCRELX, in 64-bit mode.
|
||
|
|
<samp><span class="option">-mrelax-relocations=</span><var>yes</var></samp> will generate relax relocations.
|
||
|
|
<samp><span class="option">-mrelax-relocations=</span><var>no</var></samp> will not generate relax
|
||
|
|
relocations. The default can be controlled by a configure option
|
||
|
|
<samp><span class="option">--enable-x86-relax-relocations</span></samp>.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmx86_002dused_002dnote_003d_007d-option_002c-i386-1121"></a><a name="index-g_t_0040samp_007b_002dmx86_002dused_002dnote_003d_007d-option_002c-x86_002d64-1122"></a><br><dt><code>-mx86-used-note=</code><var>no</var><dt><code>-mx86-used-note=</code><var>yes</var><dd>These options control whether the assembler should generate
|
||
|
|
GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED
|
||
|
|
GNU property notes. The default can be controlled by the
|
||
|
|
<samp><span class="option">--enable-x86-used-note</span></samp> configure option.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmevexrcig_003d_007d-option_002c-i386-1123"></a><a name="index-g_t_0040samp_007b_002dmevexrcig_003d_007d-option_002c-x86_002d64-1124"></a><br><dt><code>-mevexrcig=</code><var>rne</var><dt><code>-mevexrcig=</code><var>rd</var><dt><code>-mevexrcig=</code><var>ru</var><dt><code>-mevexrcig=</code><var>rz</var><dd>These options control how the assembler should encode SAE-only
|
||
|
|
EVEX instructions. <samp><span class="option">-mevexrcig=</span><var>rne</var></samp> will encode RC bits
|
||
|
|
of EVEX instruction with 00, which is the default.
|
||
|
|
<samp><span class="option">-mevexrcig=</span><var>rd</var></samp>, <samp><span class="option">-mevexrcig=</span><var>ru</var></samp>
|
||
|
|
and <samp><span class="option">-mevexrcig=</span><var>rz</var></samp> will encode SAE-only EVEX instructions
|
||
|
|
with 01, 10 and 11 RC bits, respectively.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dmamd64_007d-option_002c-x86_002d64-1125"></a><a name="index-g_t_0040samp_007b_002dmintel64_007d-option_002c-x86_002d64-1126"></a><br><dt><code>-mamd64</code><dt><code>-mintel64</code><dd>This option specifies that the assembler should accept only AMD64 or
|
||
|
|
Intel64 ISA in 64-bit mode. The default is to accept both.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040samp_007b_002dO0_007d-option_002c-i386-1127"></a><a name="index-g_t_0040samp_007b_002dO0_007d-option_002c-x86_002d64-1128"></a><a name="index-g_t_0040samp_007b_002dO_007d-option_002c-i386-1129"></a><a name="index-g_t_0040samp_007b_002dO_007d-option_002c-x86_002d64-1130"></a><a name="index-g_t_0040samp_007b_002dO1_007d-option_002c-i386-1131"></a><a name="index-g_t_0040samp_007b_002dO1_007d-option_002c-x86_002d64-1132"></a><a name="index-g_t_0040samp_007b_002dO2_007d-option_002c-i386-1133"></a><a name="index-g_t_0040samp_007b_002dO2_007d-option_002c-x86_002d64-1134"></a><a name="index-g_t_0040samp_007b_002dOs_007d-option_002c-i386-1135"></a><a name="index-g_t_0040samp_007b_002dOs_007d-option_002c-x86_002d64-1136"></a><br><dt><code>-O0 | -O | -O1 | -O2 | -Os</code><dd>Optimize instruction encoding with smaller instruction size. ‘<samp><span class="samp">-O</span></samp>’
|
||
|
|
and ‘<samp><span class="samp">-O1</span></samp>’ encode 64-bit register load instructions with 64-bit
|
||
|
|
immediate as 32-bit register load instructions with 31-bit or 32-bits
|
||
|
|
immediates, encode 64-bit register clearing instructions with 32-bit
|
||
|
|
register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector
|
||
|
|
register clearing instructions with 128-bit VEX vector register
|
||
|
|
clearing instructions, encode 128-bit/256-bit EVEX vector
|
||
|
|
register load/store instructions with VEX vector register load/store
|
||
|
|
instructions, and encode 128-bit/256-bit EVEX packed integer logical
|
||
|
|
instructions with 128-bit/256-bit VEX packed integer logical.
|
||
|
|
|
||
|
|
<p>‘<samp><span class="samp">-O2</span></samp>’ includes ‘<samp><span class="samp">-O1</span></samp>’ optimization plus encodes
|
||
|
|
256-bit/512-bit EVEX vector register clearing instructions with 128-bit
|
||
|
|
EVEX vector register clearing instructions. In 64-bit mode VEX encoded
|
||
|
|
instructions with commutative source operands will also have their
|
||
|
|
source operands swapped if this allows using the 2-byte VEX prefix form
|
||
|
|
instead of the 3-byte one. Certain forms of AND as well as OR with the
|
||
|
|
same (register) operand specified twice will also be changed to TEST.
|
||
|
|
|
||
|
|
<p>‘<samp><span class="samp">-Os</span></samp>’ includes ‘<samp><span class="samp">-O2</span></samp>’ optimization plus encodes 16-bit, 32-bit
|
||
|
|
and 64-bit register tests with immediate as 8-bit register test with
|
||
|
|
immediate. ‘<samp><span class="samp">-O0</span></samp>’ turns off this optimization.
|
||
|
|
|
||
|
|
</dl>
|
||
|
|
<!-- man end -->
|
||
|
|
|
||
|
|
</body></html>
|
||
|
|
|