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<h4 class="subsection">9.16.7 Memory References</h4>
<p><a name="index-i386-memory-references-1221"></a><a name="index-memory-references_002c-i386-1222"></a><a name="index-x86_002d64-memory-references-1223"></a><a name="index-memory-references_002c-x86_002d64-1224"></a>An Intel syntax indirect memory reference of the form
<pre class="smallexample"> <var>section</var>:[<var>base</var> + <var>index</var>*<var>scale</var> + <var>disp</var>]
</pre>
<p class="noindent">is translated into the AT&amp;T syntax
<pre class="smallexample"> <var>section</var>:<var>disp</var>(<var>base</var>, <var>index</var>, <var>scale</var>)
</pre>
<p class="noindent">where <var>base</var> and <var>index</var> are the optional 32-bit base and
index registers, <var>disp</var> is the optional displacement, and
<var>scale</var>, taking the values 1, 2, 4, and 8, multiplies <var>index</var>
to calculate the address of the operand. If no <var>scale</var> is
specified, <var>scale</var> is taken to be 1. <var>section</var> specifies the
optional section register for the memory operand, and may override the
default section register (see a 80386 manual for section register
defaults). Note that section overrides in AT&amp;T syntax <em>must</em>
be preceded by a &lsquo;<samp><span class="samp">%</span></samp>&rsquo;. If you specify a section override which
coincides with the default section register, <code>as</code> does <em>not</em>
output any section register override prefixes to assemble the given
instruction. Thus, section overrides can be specified to emphasize which
section register is used for a given memory operand.
<p>Here are some examples of Intel and AT&amp;T style memory references:
<dl>
<dt>AT&amp;T: &lsquo;<samp><span class="samp">-4(%ebp)</span></samp>&rsquo;, Intel: &lsquo;<samp><span class="samp">[ebp - 4]</span></samp>&rsquo;<dd><var>base</var> is &lsquo;<samp><span class="samp">%ebp</span></samp>&rsquo;; <var>disp</var> is &lsquo;<samp><span class="samp">-4</span></samp>&rsquo;. <var>section</var> is
missing, and the default section is used (&lsquo;<samp><span class="samp">%ss</span></samp>&rsquo; for addressing with
&lsquo;<samp><span class="samp">%ebp</span></samp>&rsquo; as the base register). <var>index</var>, <var>scale</var> are both missing.
<br><dt>AT&amp;T: &lsquo;<samp><span class="samp">foo(,%eax,4)</span></samp>&rsquo;, Intel: &lsquo;<samp><span class="samp">[foo + eax*4]</span></samp>&rsquo;<dd><var>index</var> is &lsquo;<samp><span class="samp">%eax</span></samp>&rsquo; (scaled by a <var>scale</var> 4); <var>disp</var> is
&lsquo;<samp><span class="samp">foo</span></samp>&rsquo;. All other fields are missing. The section register here
defaults to &lsquo;<samp><span class="samp">%ds</span></samp>&rsquo;.
<br><dt>AT&amp;T: &lsquo;<samp><span class="samp">foo(,1)</span></samp>&rsquo;; Intel &lsquo;<samp><span class="samp">[foo]</span></samp>&rsquo;<dd>This uses the value pointed to by &lsquo;<samp><span class="samp">foo</span></samp>&rsquo; as a memory operand.
Note that <var>base</var> and <var>index</var> are both missing, but there is only
<em>one</em> &lsquo;<samp><span class="samp">,</span></samp>&rsquo;. This is a syntactic exception.
<br><dt>AT&amp;T: &lsquo;<samp><span class="samp">%gs:foo</span></samp>&rsquo;; Intel &lsquo;<samp><span class="samp">gs:foo</span></samp>&rsquo;<dd>This selects the contents of the variable &lsquo;<samp><span class="samp">foo</span></samp>&rsquo; with section
register <var>section</var> being &lsquo;<samp><span class="samp">%gs</span></samp>&rsquo;.
</dl>
<p>Absolute (as opposed to PC relative) call and jump operands must be
prefixed with &lsquo;<samp><span class="samp">*</span></samp>&rsquo;. If no &lsquo;<samp><span class="samp">*</span></samp>&rsquo; is specified, <code>as</code>
always chooses PC relative addressing for jump/call labels.
<p>Any instruction that has a memory operand, but no register operand,
<em>must</em> specify its size (byte, word, long, or quadruple) with an
instruction mnemonic suffix (&lsquo;<samp><span class="samp">b</span></samp>&rsquo;, &lsquo;<samp><span class="samp">w</span></samp>&rsquo;, &lsquo;<samp><span class="samp">l</span></samp>&rsquo; or &lsquo;<samp><span class="samp">q</span></samp>&rsquo;,
respectively).
<p>The x86-64 architecture adds an RIP (instruction pointer relative)
addressing. This addressing mode is specified by using &lsquo;<samp><span class="samp">rip</span></samp>&rsquo; as a
base register. Only constant offsets are valid. For example:
<dl>
<dt>AT&amp;T: &lsquo;<samp><span class="samp">1234(%rip)</span></samp>&rsquo;, Intel: &lsquo;<samp><span class="samp">[rip + 1234]</span></samp>&rsquo;<dd>Points to the address 1234 bytes past the end of the current
instruction.
<br><dt>AT&amp;T: &lsquo;<samp><span class="samp">symbol(%rip)</span></samp>&rsquo;, Intel: &lsquo;<samp><span class="samp">[rip + symbol]</span></samp>&rsquo;<dd>Points to the <code>symbol</code> in RIP relative way, this is shorter than
the default absolute addressing.
</dl>
<p>Other addressing modes remain unchanged in x86-64 architecture, except
registers used are 64-bit instead of 32-bit.
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