155 lines
9.6 KiB
HTML
155 lines
9.6 KiB
HTML
|
<html lang="en">
|
||
|
|
<head>
|
||
|
|
<title>S12Z Addressing Modes - Using as</title>
|
||
|
|
<meta http-equiv="Content-Type" content="text/html">
|
||
|
|
<meta name="description" content="Using as">
|
||
|
|
<meta name="generator" content="makeinfo 4.13">
|
||
|
|
<link title="Top" rel="start" href="index.html#Top">
|
||
|
|
<link rel="up" href="S12Z-Syntax.html#S12Z-Syntax" title="S12Z Syntax">
|
||
|
|
<link rel="prev" href="S12Z-Syntax-Overview.html#S12Z-Syntax-Overview" title="S12Z Syntax Overview">
|
||
|
|
<link rel="next" href="S12Z-Register-Notation.html#S12Z-Register-Notation" title="S12Z Register Notation">
|
||
|
|
<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage">
|
||
|
|
<!--
|
||
|
|
This file documents the GNU Assembler "as".
|
||
|
|
|
||
|
|
Copyright (C) 1991-2019 Free Software Foundation, Inc.
|
||
|
|
|
||
|
|
Permission is granted to copy, distribute and/or modify this document
|
||
|
|
under the terms of the GNU Free Documentation License, Version 1.3
|
||
|
|
or any later version published by the Free Software Foundation;
|
||
|
|
with no Invariant Sections, with no Front-Cover Texts, and with no
|
||
|
|
Back-Cover Texts. A copy of the license is included in the
|
||
|
|
section entitled ``GNU Free Documentation License''.
|
||
|
|
|
||
|
|
-->
|
||
|
|
<meta http-equiv="Content-Style-Type" content="text/css">
|
||
|
|
<style type="text/css"><!--
|
||
|
|
pre.display { font-family:inherit }
|
||
|
|
pre.format { font-family:inherit }
|
||
|
|
pre.smalldisplay { font-family:inherit; font-size:smaller }
|
||
|
|
pre.smallformat { font-family:inherit; font-size:smaller }
|
||
|
|
pre.smallexample { font-size:smaller }
|
||
|
|
pre.smalllisp { font-size:smaller }
|
||
|
|
span.sc { font-variant:small-caps }
|
||
|
|
span.roman { font-family:serif; font-weight:normal; }
|
||
|
|
span.sansserif { font-family:sans-serif; font-weight:normal; }
|
||
|
|
--></style>
|
||
|
|
</head>
|
||
|
|
<body>
|
||
|
|
<div class="node">
|
||
|
|
<a name="S12Z-Addressing-Modes"></a>
|
||
|
|
<p>
|
||
|
|
Next: <a rel="next" accesskey="n" href="S12Z-Register-Notation.html#S12Z-Register-Notation">S12Z Register Notation</a>,
|
||
|
|
Previous: <a rel="previous" accesskey="p" href="S12Z-Syntax-Overview.html#S12Z-Syntax-Overview">S12Z Syntax Overview</a>,
|
||
|
|
Up: <a rel="up" accesskey="u" href="S12Z-Syntax.html#S12Z-Syntax">S12Z Syntax</a>
|
||
|
|
<hr>
|
||
|
|
</div>
|
||
|
|
|
||
|
|
<h5 class="subsubsection">9.24.2.2 Addressing Modes</h5>
|
||
|
|
|
||
|
|
<p><a name="index-S12Z-addressing-modes-1528"></a><a name="index-addressing-modes_002c-S12Z-1529"></a>
|
||
|
|
The following addressing modes are understood for the S12Z.
|
||
|
|
<dl>
|
||
|
|
<dt><dfn>Immediate</dfn><dd>‘<samp><span class="samp">#</span><var>number</var></samp>’
|
||
|
|
|
||
|
|
<br><dt><dfn>Immediate Bit Field</dfn><dd>‘<samp><span class="samp">#</span><var>width</var><span class="samp">:</span><var>offset</var></samp>’
|
||
|
|
|
||
|
|
<p>Bit field instructions in the immediate mode require the width and offset to
|
||
|
|
be specified.
|
||
|
|
The <var>width</var> parameter specifies the number of bits in the field.
|
||
|
|
It should be a number in the range [1,32].
|
||
|
|
<var>Offset</var> determines the position within the field where the operation
|
||
|
|
should start.
|
||
|
|
It should be a number in the range [0,31].
|
||
|
|
|
||
|
|
<br><dt><dfn>Relative</dfn><dd>‘<samp><span class="samp">*</span><var>symbol</var></samp>’, or ‘<samp><span class="samp">*[+-]</span><var>digits</var></samp>’
|
||
|
|
|
||
|
|
<p>Program counter relative addresses have a width of 15 bits.
|
||
|
|
Thus, they must be within the range [-32768, 32767].
|
||
|
|
|
||
|
|
<br><dt><dfn>Register</dfn><dd>‘<samp><var>reg</var></samp>’
|
||
|
|
|
||
|
|
<p><a name="index-register-names_002c-S12Z-1530"></a>Some instructions accept a register as an operand.
|
||
|
|
In general, <var>reg</var> may be a
|
||
|
|
data register (‘<samp><span class="samp">D0</span></samp>’, ‘<samp><span class="samp">D1</span></samp>’ <small class="dots">...</small> ‘<samp><span class="samp">D7</span></samp>’),
|
||
|
|
the ‘<samp><span class="samp">X</span></samp>’ register or the ‘<samp><span class="samp">Y</span></samp>’ register.
|
||
|
|
|
||
|
|
<p>A few instructions accept as an argument the stack pointer
|
||
|
|
register (‘<samp><span class="samp">S</span></samp>’), and/or the program counter (‘<samp><span class="samp">P</span></samp>’).
|
||
|
|
|
||
|
|
<p>Some very special instructions accept arguments which refer to the
|
||
|
|
condition code register. For these arguments the syntax is
|
||
|
|
‘<samp><span class="samp">CCR</span></samp>’, ‘<samp><span class="samp">CCH</span></samp>’ or ‘<samp><span class="samp">CCL</span></samp>’ which refer to the complete
|
||
|
|
condition code register, the condition code register high byte
|
||
|
|
and the condition code register low byte respectively.
|
||
|
|
|
||
|
|
<br><dt><dfn>Absolute Direct</dfn><dd>‘<samp><var>symbol</var></samp>’, or ‘<samp><var>digits</var></samp>’
|
||
|
|
|
||
|
|
<br><dt><dfn>Absolute Indirect</dfn><dd>‘<samp><span class="samp">[</span><var>symbol</var></samp>’, or ‘<samp><var>digits</var><span class="samp">]</span></samp>’
|
||
|
|
|
||
|
|
<br><dt><dfn>Constant Offset Indexed</dfn><dd>‘<samp><span class="samp">(</span><var>number</var><span class="samp">,</span><var>reg</var><span class="samp">)</span></samp>’
|
||
|
|
|
||
|
|
<p><var>Reg</var> may be either ‘<samp><span class="samp">X</span></samp>’, ‘<samp><span class="samp">Y</span></samp>’, ‘<samp><span class="samp">S</span></samp>’ or
|
||
|
|
‘<samp><span class="samp">P</span></samp>’ or one of the data registers ‘<samp><span class="samp">D0</span></samp>’, ‘<samp><span class="samp">D1</span></samp>’ <small class="dots">...</small>
|
||
|
|
‘<samp><span class="samp">D7</span></samp>’.
|
||
|
|
If any of the registers ‘<samp><span class="samp">D2</span></samp>’ <small class="dots">...</small> ‘<samp><span class="samp">D5</span></samp>’ are specified, then the
|
||
|
|
register value is treated as a signed value.
|
||
|
|
Otherwise it is treated as unsigned.
|
||
|
|
<var>Number</var> may be any integer in the range [-8388608,8388607].
|
||
|
|
|
||
|
|
<br><dt><dfn>Offset Indexed Indirect</dfn><dd>‘<samp><span class="samp">[</span><var>number</var><span class="samp">,</span><var>reg</var><span class="samp">]</span></samp>’
|
||
|
|
|
||
|
|
<p><var>Reg</var> may be either ‘<samp><span class="samp">X</span></samp>’, ‘<samp><span class="samp">Y</span></samp>’, ‘<samp><span class="samp">S</span></samp>’ or
|
||
|
|
‘<samp><span class="samp">P</span></samp>’.
|
||
|
|
<var>Number</var> may be any integer in the range [-8388608,8388607].
|
||
|
|
|
||
|
|
<br><dt><dfn>Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement</dfn><dd>‘<samp><span class="samp">-</span><var>reg</var></samp>’,
|
||
|
|
‘<samp><span class="samp">+</span><var>reg</var></samp>’,
|
||
|
|
‘<samp><var>reg</var><span class="samp">-</span></samp>’ or
|
||
|
|
‘<samp><var>reg</var><span class="samp">+</span></samp>’
|
||
|
|
|
||
|
|
<p>This addressing mode is typically used to access a value at an address,
|
||
|
|
and simultaneously to increment/decrement the register pointing to that
|
||
|
|
address.
|
||
|
|
Thus <var>reg</var> may be any of the 24 bit registers ‘<samp><span class="samp">X</span></samp>’, ‘<samp><span class="samp">Y</span></samp>’, or
|
||
|
|
‘<samp><span class="samp">S</span></samp>’.
|
||
|
|
Pre-increment and post-decrement are not available for
|
||
|
|
register ‘<samp><span class="samp">S</span></samp>’ (only post-increment and pre-decrement are available).
|
||
|
|
|
||
|
|
<br><dt><dfn>Register Offset Direct</dfn><dd>‘<samp><span class="samp">(</span><var>data-reg</var><span class="samp">,</span><var>reg</var><span class="samp">)</span></samp>’
|
||
|
|
|
||
|
|
<p><var>Reg</var> can be either ‘<samp><span class="samp">X</span></samp>’, ‘<samp><span class="samp">Y</span></samp>’, or ‘<samp><span class="samp">S</span></samp>’.
|
||
|
|
<var>Data-reg</var>
|
||
|
|
must be one of the data registers ‘<samp><span class="samp">D0</span></samp>’, ‘<samp><span class="samp">D1</span></samp>’ <small class="dots">...</small> ‘<samp><span class="samp">D7</span></samp>’.
|
||
|
|
If any of the registers ‘<samp><span class="samp">D2</span></samp>’ <small class="dots">...</small> ‘<samp><span class="samp">D5</span></samp>’ are specified, then
|
||
|
|
the register value is treated as a signed value.
|
||
|
|
Otherwise it is treated as unsigned.
|
||
|
|
|
||
|
|
<br><dt><dfn>Register Offset Indirect</dfn><dd>‘<samp><span class="samp">[</span><var>data-reg</var><span class="samp">,</span><var>reg</var><span class="samp">]</span></samp>’
|
||
|
|
|
||
|
|
<p><var>Reg</var> can be either ‘<samp><span class="samp">X</span></samp>’ or ‘<samp><span class="samp">Y</span></samp>’.
|
||
|
|
<var>Data-reg</var>
|
||
|
|
must be one of the data registers ‘<samp><span class="samp">D0</span></samp>’, ‘<samp><span class="samp">D1</span></samp>’ <small class="dots">...</small> ‘<samp><span class="samp">D7</span></samp>’.
|
||
|
|
If any of the registers ‘<samp><span class="samp">D2</span></samp>’ <small class="dots">...</small> ‘<samp><span class="samp">D5</span></samp>’ are specified, then
|
||
|
|
the register value is treated as a signed value.
|
||
|
|
Otherwise it is treated as unsigned.
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
<p>For example:
|
||
|
|
|
||
|
|
<pre class="smallexample"> trap #197 ;; Immediate mode
|
||
|
|
bra *+49 ;; Relative mode
|
||
|
|
bra .L0 ;; ditto
|
||
|
|
jmp 0xFE0034 ;; Absolute direct mode
|
||
|
|
jmp [0xFD0012] ;; Absolute indirect mode
|
||
|
|
inc.b (4,x) ;; Constant offset indexed mode
|
||
|
|
jsr (45, d0) ;; ditto
|
||
|
|
dec.w [4,y] ;; Constant offset indexed indirect mode
|
||
|
|
clr.p (-s) ;; Pre-decrement mode
|
||
|
|
neg.l (d0, s) ;; Register offset direct mode
|
||
|
|
com.b [d1, x] ;; Register offset indirect mode
|
||
|
|
psh cch ;; Register mode
|
||
|
|
</pre>
|
||
|
|
</body></html>
|
||
|
|
|