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483 lines
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<head>
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<title>MIPS Options - Using as</title>
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<meta name="description" content="Using as">
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="MIPS_002dDependent.html#MIPS_002dDependent" title="MIPS-Dependent">
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<link rel="next" href="MIPS-Macros.html#MIPS-Macros" title="MIPS Macros">
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<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage">
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<!--
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This file documents the GNU Assembler "as".
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Copyright (C) 1991-2019 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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Back-Cover Texts. A copy of the license is included in the
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section entitled ``GNU Free Documentation License''.
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--></style>
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</head>
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<body>
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<div class="node">
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<a name="MIPS-Options"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="MIPS-Macros.html#MIPS-Macros">MIPS Macros</a>,
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Up: <a rel="up" accesskey="u" href="MIPS_002dDependent.html#MIPS_002dDependent">MIPS-Dependent</a>
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<hr>
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</div>
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<h4 class="subsection">9.27.1 Assembler options</h4>
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<p>The MIPS configurations of <span class="sc">gnu</span> <code>as</code> support these
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special options:
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<a name="index-g_t_0040code_007b_002dG_007d-option-_0028MIPS_0029-1555"></a>
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<dl><dt><code>-G </code><var>num</var><dd>Set the “small data” limit to <var>n</var> bytes. The default limit is 8 bytes.
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See <a href="MIPS-Small-Data.html#MIPS-Small-Data">Controlling the use of small data accesses</a>.
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<p><a name="index-g_t_0040code_007b_002dEB_007d-option-_0028MIPS_0029-1556"></a><a name="index-g_t_0040code_007b_002dEL_007d-option-_0028MIPS_0029-1557"></a><a name="index-MIPS-big_002dendian-output-1558"></a><a name="index-MIPS-little_002dendian-output-1559"></a><a name="index-big_002dendian-output_002c-MIPS-1560"></a><a name="index-little_002dendian-output_002c-MIPS-1561"></a><br><dt><code>-EB</code><dt><code>-EL</code><dd>Any MIPS configuration of <code>as</code> can select big-endian or
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little-endian output at run time (unlike the other <span class="sc">gnu</span> development
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tools, which must be configured for one or the other). Use ‘<samp><span class="samp">-EB</span></samp>’
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to select big-endian output, and ‘<samp><span class="samp">-EL</span></samp>’ for little-endian.
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<br><dt><code>-KPIC</code><dd><a name="index-PIC-selection_002c-MIPS-1562"></a><a name="index-g_t_0040option_007b_002dKPIC_007d-option_002c-MIPS-1563"></a>Generate SVR4-style PIC. This option tells the assembler to generate
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SVR4-style position-independent macro expansions. It also tells the
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assembler to mark the output file as PIC.
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<br><dt><code>-mvxworks-pic</code><dd><a name="index-g_t_0040option_007b_002dmvxworks_002dpic_007d-option_002c-MIPS-1564"></a>Generate VxWorks PIC. This option tells the assembler to generate
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VxWorks-style position-independent macro expansions.
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<p><a name="index-MIPS-architecture-options-1565"></a><br><dt><code>-mips1</code><dt><code>-mips2</code><dt><code>-mips3</code><dt><code>-mips4</code><dt><code>-mips5</code><dt><code>-mips32</code><dt><code>-mips32r2</code><dt><code>-mips32r3</code><dt><code>-mips32r5</code><dt><code>-mips32r6</code><dt><code>-mips64</code><dt><code>-mips64r2</code><dt><code>-mips64r3</code><dt><code>-mips64r5</code><dt><code>-mips64r6</code><dd>Generate code for a particular MIPS Instruction Set Architecture level.
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‘<samp><span class="samp">-mips1</span></samp>’ corresponds to the R2000 and R3000 processors,
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‘<samp><span class="samp">-mips2</span></samp>’ to the R6000 processor, ‘<samp><span class="samp">-mips3</span></samp>’ to the
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R4000 processor, and ‘<samp><span class="samp">-mips4</span></samp>’ to the R8000 and R10000 processors.
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‘<samp><span class="samp">-mips5</span></samp>’, ‘<samp><span class="samp">-mips32</span></samp>’, ‘<samp><span class="samp">-mips32r2</span></samp>’, ‘<samp><span class="samp">-mips32r3</span></samp>’,
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‘<samp><span class="samp">-mips32r5</span></samp>’, ‘<samp><span class="samp">-mips32r6</span></samp>’, ‘<samp><span class="samp">-mips64</span></samp>’, ‘<samp><span class="samp">-mips64r2</span></samp>’,
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‘<samp><span class="samp">-mips64r3</span></samp>’, ‘<samp><span class="samp">-mips64r5</span></samp>’, and ‘<samp><span class="samp">-mips64r6</span></samp>’ correspond to
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generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32
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Release 5, MIPS32 Release 6, MIPS64, and MIPS64 Release 2, MIPS64
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Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors,
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respectively. You can also switch instruction sets during the assembly;
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see <a href="MIPS-ISA.html#MIPS-ISA">Directives to override the ISA level</a>.
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<br><dt><code>-mgp32</code><dt><code>-mfp32</code><dd>Some macros have different expansions for 32-bit and 64-bit registers.
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The register sizes are normally inferred from the ISA and ABI, but these
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flags force a certain group of registers to be treated as 32 bits wide at
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all times. ‘<samp><span class="samp">-mgp32</span></samp>’ controls the size of general-purpose registers
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and ‘<samp><span class="samp">-mfp32</span></samp>’ controls the size of floating-point registers.
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<p>The <code>.set gp=32</code> and <code>.set fp=32</code> directives allow the size
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of registers to be changed for parts of an object. The default value is
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restored by <code>.set gp=default</code> and <code>.set fp=default</code>.
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<p>On some MIPS variants there is a 32-bit mode flag; when this flag is
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set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
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save the 32-bit registers on a context switch, so it is essential never
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to use the 64-bit registers.
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<br><dt><code>-mgp64</code><dt><code>-mfp64</code><dd>Assume that 64-bit registers are available. This is provided in the
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interests of symmetry with ‘<samp><span class="samp">-mgp32</span></samp>’ and ‘<samp><span class="samp">-mfp32</span></samp>’.
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<p>The <code>.set gp=64</code> and <code>.set fp=64</code> directives allow the size
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of registers to be changed for parts of an object. The default value is
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restored by <code>.set gp=default</code> and <code>.set fp=default</code>.
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<br><dt><code>-mfpxx</code><dd>Make no assumptions about whether 32-bit or 64-bit floating-point
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registers are available. This is provided to support having modules
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compatible with either ‘<samp><span class="samp">-mfp32</span></samp>’ or ‘<samp><span class="samp">-mfp64</span></samp>’. This option can
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only be used with MIPS II and above.
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<p>The <code>.set fp=xx</code> directive allows a part of an object to be marked
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as not making assumptions about 32-bit or 64-bit FP registers. The
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default value is restored by <code>.set fp=default</code>.
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<br><dt><code>-modd-spreg</code><dt><code>-mno-odd-spreg</code><dd>Enable use of floating-point operations on odd-numbered single-precision
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registers when supported by the ISA. ‘<samp><span class="samp">-mfpxx</span></samp>’ implies
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‘<samp><span class="samp">-mno-odd-spreg</span></samp>’, otherwise the default is ‘<samp><span class="samp">-modd-spreg</span></samp>’
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<br><dt><code>-mips16</code><dt><code>-no-mips16</code><dd>Generate code for the MIPS 16 processor. This is equivalent to putting
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<code>.module mips16</code> at the start of the assembly file. ‘<samp><span class="samp">-no-mips16</span></samp>’
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turns off this option.
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<br><dt><code>-mmips16e2</code><dt><code>-mno-mips16e2</code><dd>Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent
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to putting <code>.module mips16e2</code> at the start of the assembly file.
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‘<samp><span class="samp">-mno-mips16e2</span></samp>’ turns off this option.
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<br><dt><code>-mmicromips</code><dt><code>-mno-micromips</code><dd>Generate code for the microMIPS processor. This is equivalent to putting
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<code>.module micromips</code> at the start of the assembly file.
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‘<samp><span class="samp">-mno-micromips</span></samp>’ turns off this option. This is equivalent to putting
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<code>.module nomicromips</code> at the start of the assembly file.
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<br><dt><code>-msmartmips</code><dt><code>-mno-smartmips</code><dd>Enables the SmartMIPS extensions to the MIPS32 instruction set, which
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provides a number of new instructions which target smartcard and
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cryptographic applications. This is equivalent to putting
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<code>.module smartmips</code> at the start of the assembly file.
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‘<samp><span class="samp">-mno-smartmips</span></samp>’ turns off this option.
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<br><dt><code>-mips3d</code><dt><code>-no-mips3d</code><dd>Generate code for the MIPS-3D Application Specific Extension.
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This tells the assembler to accept MIPS-3D instructions.
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‘<samp><span class="samp">-no-mips3d</span></samp>’ turns off this option.
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<br><dt><code>-mdmx</code><dt><code>-no-mdmx</code><dd>Generate code for the MDMX Application Specific Extension.
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This tells the assembler to accept MDMX instructions.
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‘<samp><span class="samp">-no-mdmx</span></samp>’ turns off this option.
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<br><dt><code>-mdsp</code><dt><code>-mno-dsp</code><dd>Generate code for the DSP Release 1 Application Specific Extension.
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This tells the assembler to accept DSP Release 1 instructions.
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‘<samp><span class="samp">-mno-dsp</span></samp>’ turns off this option.
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<br><dt><code>-mdspr2</code><dt><code>-mno-dspr2</code><dd>Generate code for the DSP Release 2 Application Specific Extension.
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This option implies ‘<samp><span class="samp">-mdsp</span></samp>’.
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This tells the assembler to accept DSP Release 2 instructions.
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‘<samp><span class="samp">-mno-dspr2</span></samp>’ turns off this option.
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<br><dt><code>-mdspr3</code><dt><code>-mno-dspr3</code><dd>Generate code for the DSP Release 3 Application Specific Extension.
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This option implies ‘<samp><span class="samp">-mdsp</span></samp>’ and ‘<samp><span class="samp">-mdspr2</span></samp>’.
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This tells the assembler to accept DSP Release 3 instructions.
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‘<samp><span class="samp">-mno-dspr3</span></samp>’ turns off this option.
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<br><dt><code>-mmt</code><dt><code>-mno-mt</code><dd>Generate code for the MT Application Specific Extension.
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This tells the assembler to accept MT instructions.
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‘<samp><span class="samp">-mno-mt</span></samp>’ turns off this option.
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<br><dt><code>-mmcu</code><dt><code>-mno-mcu</code><dd>Generate code for the MCU Application Specific Extension.
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This tells the assembler to accept MCU instructions.
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‘<samp><span class="samp">-mno-mcu</span></samp>’ turns off this option.
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<br><dt><code>-mmsa</code><dt><code>-mno-msa</code><dd>Generate code for the MIPS SIMD Architecture Extension.
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This tells the assembler to accept MSA instructions.
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‘<samp><span class="samp">-mno-msa</span></samp>’ turns off this option.
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<br><dt><code>-mxpa</code><dt><code>-mno-xpa</code><dd>Generate code for the MIPS eXtended Physical Address (XPA) Extension.
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This tells the assembler to accept XPA instructions.
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‘<samp><span class="samp">-mno-xpa</span></samp>’ turns off this option.
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<br><dt><code>-mvirt</code><dt><code>-mno-virt</code><dd>Generate code for the Virtualization Application Specific Extension.
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This tells the assembler to accept Virtualization instructions.
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‘<samp><span class="samp">-mno-virt</span></samp>’ turns off this option.
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<br><dt><code>-mcrc</code><dt><code>-mno-crc</code><dd>Generate code for the cyclic redundancy check (CRC) Application Specific
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Extension. This tells the assembler to accept CRC instructions.
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‘<samp><span class="samp">-mno-crc</span></samp>’ turns off this option.
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<br><dt><code>-mginv</code><dt><code>-mno-ginv</code><dd>Generate code for the Global INValidate (GINV) Application Specific
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Extension. This tells the assembler to accept GINV instructions.
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‘<samp><span class="samp">-mno-ginv</span></samp>’ turns off this option.
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<br><dt><code>-mloongson-mmi</code><dt><code>-mno-loongson-mmi</code><dd>Generate code for the Loongson MultiMedia extensions Instructions (MMI)
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Application Specific Extension. This tells the assembler to accept MMI
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instructions.
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‘<samp><span class="samp">-mno-loongson-mmi</span></samp>’ turns off this option.
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<br><dt><code>-mloongson-cam</code><dt><code>-mno-loongson-cam</code><dd>Generate code for the Loongson Content Address Memory (CAM)
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Application Specific Extension. This tells the assembler to accept CAM
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instructions.
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‘<samp><span class="samp">-mno-loongson-cam</span></samp>’ turns off this option.
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<br><dt><code>-mloongson-ext</code><dt><code>-mno-loongson-ext</code><dd>Generate code for the Loongson EXTensions (EXT) instructions
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Application Specific Extension. This tells the assembler to accept EXT
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instructions.
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‘<samp><span class="samp">-mno-loongson-ext</span></samp>’ turns off this option.
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<br><dt><code>-mloongson-ext2</code><dt><code>-mno-loongson-ext2</code><dd>Generate code for the Loongson EXTensions R2 (EXT2) instructions
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Application Specific Extension. This tells the assembler to accept EXT2
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instructions.
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‘<samp><span class="samp">-mno-loongson-ext2</span></samp>’ turns off this option.
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<br><dt><code>-minsn32</code><dt><code>-mno-insn32</code><dd>Only use 32-bit instruction encodings when generating code for the
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microMIPS processor. This option inhibits the use of any 16-bit
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instructions. This is equivalent to putting <code>.set insn32</code> at
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the start of the assembly file. ‘<samp><span class="samp">-mno-insn32</span></samp>’ turns off this
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option. This is equivalent to putting <code>.set noinsn32</code> at the
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start of the assembly file. By default ‘<samp><span class="samp">-mno-insn32</span></samp>’ is
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selected, allowing all instructions to be used.
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<br><dt><code>-mfix7000</code><dt><code>-mno-fix7000</code><dd>Cause nops to be inserted if the read of the destination register
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of an mfhi or mflo instruction occurs in the following two instructions.
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<br><dt><code>-mfix-rm7000</code><dt><code>-mno-fix-rm7000</code><dd>Cause nops to be inserted if a dmult or dmultu instruction is
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followed by a load instruction.
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<br><dt><code>-mfix-loongson2f-jump</code><dt><code>-mno-fix-loongson2f-jump</code><dd>Eliminate instruction fetch from outside 256M region to work around the
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Loongson2F ‘<samp><span class="samp">jump</span></samp>’ instructions. Without it, under extreme cases,
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the kernel may crash. The issue has been solved in latest processor
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batches, but this fix has no side effect to them.
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<br><dt><code>-mfix-loongson2f-nop</code><dt><code>-mno-fix-loongson2f-nop</code><dd>Replace nops by <code>or at,at,zero</code> to work around the Loongson2F
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‘<samp><span class="samp">nop</span></samp>’ errata. Without it, under extreme cases, the CPU might
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deadlock. The issue has been solved in later Loongson2F batches, but
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this fix has no side effect to them.
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<br><dt><code>-mfix-loongson3-llsc</code><dt><code>-mno-fix-loongson3-llsc</code><dd>Insert ‘<samp><span class="samp">sync</span></samp>’ before ‘<samp><span class="samp">ll</span></samp>’ and ‘<samp><span class="samp">lld</span></samp>’ to work around
|
||
|
|
Loongson3 LLSC errata. Without it, under extrame cases, the CPU might
|
||
|
|
deadlock. The default can be controlled by the
|
||
|
|
<samp><span class="option">--enable-mips-fix-loongson3-llsc=[yes|no]</span></samp> configure option.
|
||
|
|
|
||
|
|
<br><dt><code>-mfix-vr4120</code><dt><code>-mno-fix-vr4120</code><dd>Insert nops to work around certain VR4120 errata. This option is
|
||
|
|
intended to be used on GCC-generated code: it is not designed to catch
|
||
|
|
all problems in hand-written assembler code.
|
||
|
|
|
||
|
|
<br><dt><code>-mfix-vr4130</code><dt><code>-mno-fix-vr4130</code><dd>Insert nops to work around the VR4130 ‘<samp><span class="samp">mflo</span></samp>’/‘<samp><span class="samp">mfhi</span></samp>’ errata.
|
||
|
|
|
||
|
|
<br><dt><code>-mfix-24k</code><dt><code>-mno-fix-24k</code><dd>Insert nops to work around the 24K ‘<samp><span class="samp">eret</span></samp>’/‘<samp><span class="samp">deret</span></samp>’ errata.
|
||
|
|
|
||
|
|
<br><dt><code>-mfix-cn63xxp1</code><dt><code>-mno-fix-cn63xxp1</code><dd>Replace <code>pref</code> hints 0 - 4 and 6 - 24 with hint 28 to work around
|
||
|
|
certain CN63XXP1 errata.
|
||
|
|
|
||
|
|
<br><dt><code>-mfix-r5900</code><dt><code>-mno-fix-r5900</code><dd>Do not attempt to schedule the preceding instruction into the delay slot
|
||
|
|
of a branch instruction placed at the end of a short loop of six
|
||
|
|
instructions or fewer and always schedule a <code>nop</code> instruction there
|
||
|
|
instead. The short loop bug under certain conditions causes loops to
|
||
|
|
execute only once or twice, due to a hardware bug in the R5900 chip.
|
||
|
|
|
||
|
|
<br><dt><code>-m4010</code><dt><code>-no-m4010</code><dd>Generate code for the LSI R4010 chip. This tells the assembler to
|
||
|
|
accept the R4010-specific instructions (‘<samp><span class="samp">addciu</span></samp>’, ‘<samp><span class="samp">ffc</span></samp>’,
|
||
|
|
etc.), and to not schedule ‘<samp><span class="samp">nop</span></samp>’ instructions around accesses to
|
||
|
|
the ‘<samp><span class="samp">HI</span></samp>’ and ‘<samp><span class="samp">LO</span></samp>’ registers. ‘<samp><span class="samp">-no-m4010</span></samp>’ turns off this
|
||
|
|
option.
|
||
|
|
|
||
|
|
<br><dt><code>-m4650</code><dt><code>-no-m4650</code><dd>Generate code for the MIPS R4650 chip. This tells the assembler to accept
|
||
|
|
the ‘<samp><span class="samp">mad</span></samp>’ and ‘<samp><span class="samp">madu</span></samp>’ instruction, and to not schedule ‘<samp><span class="samp">nop</span></samp>’
|
||
|
|
instructions around accesses to the ‘<samp><span class="samp">HI</span></samp>’ and ‘<samp><span class="samp">LO</span></samp>’ registers.
|
||
|
|
‘<samp><span class="samp">-no-m4650</span></samp>’ turns off this option.
|
||
|
|
|
||
|
|
<br><dt><code>-m3900</code><dt><code>-no-m3900</code><dt><code>-m4100</code><dt><code>-no-m4100</code><dd>For each option ‘<samp><span class="samp">-m</span><var>nnnn</var></samp>’, generate code for the MIPS
|
||
|
|
R<var>nnnn</var> chip. This tells the assembler to accept instructions
|
||
|
|
specific to that chip, and to schedule for that chip's hazards.
|
||
|
|
|
||
|
|
<br><dt><code>-march=</code><var>cpu</var><dd>Generate code for a particular MIPS CPU. It is exactly equivalent to
|
||
|
|
‘<samp><span class="samp">-m</span><var>cpu</var></samp>’, except that there are more value of <var>cpu</var>
|
||
|
|
understood. Valid <var>cpu</var> value are:
|
||
|
|
|
||
|
|
<blockquote>
|
||
|
|
2000,
|
||
|
|
3000,
|
||
|
|
3900,
|
||
|
|
4000,
|
||
|
|
4010,
|
||
|
|
4100,
|
||
|
|
4111,
|
||
|
|
vr4120,
|
||
|
|
vr4130,
|
||
|
|
vr4181,
|
||
|
|
4300,
|
||
|
|
4400,
|
||
|
|
4600,
|
||
|
|
4650,
|
||
|
|
5000,
|
||
|
|
rm5200,
|
||
|
|
rm5230,
|
||
|
|
rm5231,
|
||
|
|
rm5261,
|
||
|
|
rm5721,
|
||
|
|
vr5400,
|
||
|
|
vr5500,
|
||
|
|
6000,
|
||
|
|
rm7000,
|
||
|
|
8000,
|
||
|
|
rm9000,
|
||
|
|
10000,
|
||
|
|
12000,
|
||
|
|
14000,
|
||
|
|
16000,
|
||
|
|
4kc,
|
||
|
|
4km,
|
||
|
|
4kp,
|
||
|
|
4ksc,
|
||
|
|
4kec,
|
||
|
|
4kem,
|
||
|
|
4kep,
|
||
|
|
4ksd,
|
||
|
|
m4k,
|
||
|
|
m4kp,
|
||
|
|
m14k,
|
||
|
|
m14kc,
|
||
|
|
m14ke,
|
||
|
|
m14kec,
|
||
|
|
24kc,
|
||
|
|
24kf2_1,
|
||
|
|
24kf,
|
||
|
|
24kf1_1,
|
||
|
|
24kec,
|
||
|
|
24kef2_1,
|
||
|
|
24kef,
|
||
|
|
24kef1_1,
|
||
|
|
34kc,
|
||
|
|
34kf2_1,
|
||
|
|
34kf,
|
||
|
|
34kf1_1,
|
||
|
|
34kn,
|
||
|
|
74kc,
|
||
|
|
74kf2_1,
|
||
|
|
74kf,
|
||
|
|
74kf1_1,
|
||
|
|
74kf3_2,
|
||
|
|
1004kc,
|
||
|
|
1004kf2_1,
|
||
|
|
1004kf,
|
||
|
|
1004kf1_1,
|
||
|
|
interaptiv,
|
||
|
|
interaptiv-mr2,
|
||
|
|
m5100,
|
||
|
|
m5101,
|
||
|
|
p5600,
|
||
|
|
5kc,
|
||
|
|
5kf,
|
||
|
|
20kc,
|
||
|
|
25kf,
|
||
|
|
sb1,
|
||
|
|
sb1a,
|
||
|
|
i6400,
|
||
|
|
i6500,
|
||
|
|
p6600,
|
||
|
|
loongson2e,
|
||
|
|
loongson2f,
|
||
|
|
gs464,
|
||
|
|
gs464e,
|
||
|
|
gs264e,
|
||
|
|
octeon,
|
||
|
|
octeon+,
|
||
|
|
octeon2,
|
||
|
|
octeon3,
|
||
|
|
xlr,
|
||
|
|
xlp
|
||
|
|
</blockquote>
|
||
|
|
|
||
|
|
<p>For compatibility reasons, ‘<samp><var>n</var><span class="samp">x</span></samp>’ and ‘<samp><var>b</var><span class="samp">fx</span></samp>’ are
|
||
|
|
accepted as synonyms for ‘<samp><var>n</var><span class="samp">f1_1</span></samp>’. These values are
|
||
|
|
deprecated.
|
||
|
|
|
||
|
|
<br><dt><code>-mtune=</code><var>cpu</var><dd>Schedule and tune for a particular MIPS CPU. Valid <var>cpu</var> values are
|
||
|
|
identical to ‘<samp><span class="samp">-march=</span><var>cpu</var></samp>’.
|
||
|
|
|
||
|
|
<br><dt><code>-mabi=</code><var>abi</var><dd>Record which ABI the source code uses. The recognized arguments
|
||
|
|
are: ‘<samp><span class="samp">32</span></samp>’, ‘<samp><span class="samp">n32</span></samp>’, ‘<samp><span class="samp">o64</span></samp>’, ‘<samp><span class="samp">64</span></samp>’ and ‘<samp><span class="samp">eabi</span></samp>’.
|
||
|
|
|
||
|
|
<br><dt><code>-msym32</code><dt><code>-mno-sym32</code><dd><a name="index-g_t_002dmsym32-1566"></a><a name="index-g_t_002dmno_002dsym32-1567"></a>Equivalent to adding <code>.set sym32</code> or <code>.set nosym32</code> to
|
||
|
|
the beginning of the assembler input. See <a href="MIPS-Symbol-Sizes.html#MIPS-Symbol-Sizes">MIPS Symbol Sizes</a>.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040code_007b_002dnocpp_007d-ignored-_0028MIPS_0029-1568"></a><br><dt><code>-nocpp</code><dd>This option is ignored. It is accepted for command-line compatibility with
|
||
|
|
other assemblers, which use it to turn off C style preprocessing. With
|
||
|
|
<span class="sc">gnu</span> <code>as</code>, there is no need for ‘<samp><span class="samp">-nocpp</span></samp>’, because the
|
||
|
|
<span class="sc">gnu</span> assembler itself never runs the C preprocessor.
|
||
|
|
|
||
|
|
<br><dt><code>-msoft-float</code><dt><code>-mhard-float</code><dd>Disable or enable floating-point instructions. Note that by default
|
||
|
|
floating-point instructions are always allowed even with CPU targets
|
||
|
|
that don't have support for these instructions.
|
||
|
|
|
||
|
|
<br><dt><code>-msingle-float</code><dt><code>-mdouble-float</code><dd>Disable or enable double-precision floating-point operations. Note
|
||
|
|
that by default double-precision floating-point operations are always
|
||
|
|
allowed even with CPU targets that don't have support for these
|
||
|
|
operations.
|
||
|
|
|
||
|
|
<br><dt><code>--construct-floats</code><dt><code>--no-construct-floats</code><dd>The <code>--no-construct-floats</code> option disables the construction of
|
||
|
|
double width floating point constants by loading the two halves of the
|
||
|
|
value into the two single width floating point registers that make up
|
||
|
|
the double width register. This feature is useful if the processor
|
||
|
|
support the FR bit in its status register, and this bit is known (by
|
||
|
|
the programmer) to be set. This bit prevents the aliasing of the double
|
||
|
|
width register by the single width registers.
|
||
|
|
|
||
|
|
<p>By default <code>--construct-floats</code> is selected, allowing construction
|
||
|
|
of these floating point constants.
|
||
|
|
|
||
|
|
<br><dt><code>--relax-branch</code><dt><code>--no-relax-branch</code><dd>The ‘<samp><span class="samp">--relax-branch</span></samp>’ option enables the relaxation of out-of-range
|
||
|
|
branches. Any branches whose target cannot be reached directly are
|
||
|
|
converted to a small instruction sequence including an inverse-condition
|
||
|
|
branch to the physically next instruction, and a jump to the original
|
||
|
|
target is inserted between the two instructions. In PIC code the jump
|
||
|
|
will involve further instructions for address calculation.
|
||
|
|
|
||
|
|
<p>The <code>BC1ANY2F</code>, <code>BC1ANY2T</code>, <code>BC1ANY4F</code>, <code>BC1ANY4T</code>,
|
||
|
|
<code>BPOSGE32</code> and <code>BPOSGE64</code> instructions are excluded from
|
||
|
|
relaxation, because they have no complementing counterparts. They could
|
||
|
|
be relaxed with the use of a longer sequence involving another branch,
|
||
|
|
however this has not been implemented and if their target turns out of
|
||
|
|
reach, they produce an error even if branch relaxation is enabled.
|
||
|
|
|
||
|
|
<p>Also no MIPS16 branches are ever relaxed.
|
||
|
|
|
||
|
|
<p>By default ‘<samp><span class="samp">--no-relax-branch</span></samp>’ is selected, causing any out-of-range
|
||
|
|
branches to produce an error.
|
||
|
|
|
||
|
|
<br><dt><code>-mignore-branch-isa</code><dt><code>-mno-ignore-branch-isa</code><dd>Ignore branch checks for invalid transitions between ISA modes.
|
||
|
|
|
||
|
|
<p>The semantics of branches does not provide for an ISA mode switch, so in
|
||
|
|
most cases the ISA mode a branch has been encoded for has to be the same
|
||
|
|
as the ISA mode of the branch's target label. If the ISA modes do not
|
||
|
|
match, then such a branch, if taken, will cause the ISA mode to remain
|
||
|
|
unchanged and instructions that follow will be executed in the wrong ISA
|
||
|
|
mode causing the program to misbehave or crash.
|
||
|
|
|
||
|
|
<p>In the case of the <code>BAL</code> instruction it may be possible to relax
|
||
|
|
it to an equivalent <code>JALX</code> instruction so that the ISA mode is
|
||
|
|
switched at the run time as required. For other branches no relaxation
|
||
|
|
is possible and therefore GAS has checks implemented that verify in
|
||
|
|
branch assembly that the two ISA modes match, and report an error
|
||
|
|
otherwise so that the problem with code can be diagnosed at the assembly
|
||
|
|
time rather than at the run time.
|
||
|
|
|
||
|
|
<p>However some assembly code, including generated code produced by some
|
||
|
|
versions of GCC, may incorrectly include branches to data labels, which
|
||
|
|
appear to require a mode switch but are either dead or immediately
|
||
|
|
followed by valid instructions encoded for the same ISA the branch has
|
||
|
|
been encoded for. While not strictly correct at the source level such
|
||
|
|
code will execute as intended, so to help with these cases
|
||
|
|
‘<samp><span class="samp">-mignore-branch-isa</span></samp>’ is supported which disables ISA mode checks
|
||
|
|
for branches.
|
||
|
|
|
||
|
|
<p>By default ‘<samp><span class="samp">-mno-ignore-branch-isa</span></samp>’ is selected, causing any invalid
|
||
|
|
branch requiring a transition between ISA modes to produce an error.
|
||
|
|
|
||
|
|
<p><a name="index-g_t_0040option_007b_002dmnan_003d_007d-command_002dline-option_002c-MIPS-1569"></a><br><dt><code>-mnan=</code><var>encoding</var><dd>This option indicates whether the source code uses the IEEE 2008
|
||
|
|
NaN encoding (<samp><span class="option">-mnan=2008</span></samp>) or the original MIPS encoding
|
||
|
|
(<samp><span class="option">-mnan=legacy</span></samp>). It is equivalent to adding a <code>.nan</code>
|
||
|
|
directive to the beginning of the source file. See <a href="MIPS-NaN-Encodings.html#MIPS-NaN-Encodings">MIPS NaN Encodings</a>.
|
||
|
|
|
||
|
|
<p><samp><span class="option">-mnan=legacy</span></samp> is the default if no <samp><span class="option">-mnan</span></samp> option or
|
||
|
|
<code>.nan</code> directive is used.
|
||
|
|
|
||
|
|
<br><dt><code>--trap</code><dt><code>--no-break</code><dd><!-- FIXME! (1) reflect these options (next item too) in option summaries; -->
|
||
|
|
<!-- (2) stop teasing, say _which_ instructions expanded _how_. -->
|
||
|
|
<code>as</code> automatically macro expands certain division and
|
||
|
|
multiplication instructions to check for overflow and division by zero. This
|
||
|
|
option causes <code>as</code> to generate code to take a trap exception
|
||
|
|
rather than a break exception when an error is detected. The trap instructions
|
||
|
|
are only supported at Instruction Set Architecture level 2 and higher.
|
||
|
|
|
||
|
|
<br><dt><code>--break</code><dt><code>--no-trap</code><dd>Generate code to take a break exception rather than a trap exception when an
|
||
|
|
error is detected. This is the default.
|
||
|
|
|
||
|
|
<br><dt><code>-mpdr</code><dt><code>-mno-pdr</code><dd>Control generation of <code>.pdr</code> sections. Off by default on IRIX, on
|
||
|
|
elsewhere.
|
||
|
|
|
||
|
|
<br><dt><code>-mshared</code><dt><code>-mno-shared</code><dd>When generating code using the Unix calling conventions (selected by
|
||
|
|
‘<samp><span class="samp">-KPIC</span></samp>’ or ‘<samp><span class="samp">-mcall_shared</span></samp>’), gas will normally generate code
|
||
|
|
which can go into a shared library. The ‘<samp><span class="samp">-mno-shared</span></samp>’ option
|
||
|
|
tells gas to generate code which uses the calling convention, but can
|
||
|
|
not go into a shared library. The resulting code is slightly more
|
||
|
|
efficient. This option only affects the handling of the
|
||
|
|
‘<samp><span class="samp">.cpload</span></samp>’ and ‘<samp><span class="samp">.cpsetup</span></samp>’ pseudo-ops.
|
||
|
|
</dl>
|
||
|
|
|
||
|
|
</body></html>
|
||
|
|
|