94 lines
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94 lines
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<title>MIPS FP ABI Variants - Using as</title>
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<link rel="up" href="MIPS-FP-ABIs.html#MIPS-FP-ABIs" title="MIPS FP ABIs">
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<link rel="prev" href="MIPS-FP-ABI-History.html#MIPS-FP-ABI-History" title="MIPS FP ABI History">
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<!--
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This file documents the GNU Assembler "as".
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Copyright (C) 1991-2019 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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Back-Cover Texts. A copy of the license is included in the
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<div class="node">
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<a name="MIPS-FP-ABI-Variants"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="MIPS-FP-ABI-Selection.html#MIPS-FP-ABI-Selection">MIPS FP ABI Selection</a>,
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Previous: <a rel="previous" accesskey="p" href="MIPS-FP-ABI-History.html#MIPS-FP-ABI-History">MIPS FP ABI History</a>,
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Up: <a rel="up" accesskey="u" href="MIPS-FP-ABIs.html#MIPS-FP-ABIs">MIPS FP ABIs</a>
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<hr>
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</div>
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<h5 class="subsubsection">9.27.9.2 Supported FP ABIs</h5>
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<p>The supported floating-point ABI variants are:
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<dl>
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<dt><code>0 - No floating-point</code><dd>This variant is used to indicate that floating-point is not used within
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the module at all and therefore has no impact on the ABI. This is the
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default.
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<br><dt><code>1 - Double-precision</code><dd>This variant indicates that double-precision support is used. For 64-bit
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ABIs this means that 64-bit wide floating-point registers are required.
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For 32-bit ABIs this means that 32-bit wide floating-point registers are
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required and double-precision operations use pairs of registers.
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<br><dt><code>2 - Single-precision</code><dd>This variant indicates that single-precision support is used. Double
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precision operations will be supported via soft-float routines.
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<br><dt><code>3 - Soft-float</code><dd>This variant indicates that although floating-point support is used all
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operations are emulated in software. This means the ABI is modified to
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pass all floating-point data in general-purpose registers.
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<br><dt><code>4 - Deprecated</code><dd>This variant existed as an initial attempt at supporting 64-bit wide
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floating-point registers for O32 ABI on a MIPS32r2 CPU. This has been
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superseded by 5, 6 and 7.
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<br><dt><code>5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU</code><dd>This variant is used by 32-bit ABIs to indicate that the floating-point
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code in the module has been designed to operate correctly with either
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32-bit wide or 64-bit wide floating-point registers. Double-precision
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support is used. Only O32 currently supports this variant and requires
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a minimum architecture of MIPS II.
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<br><dt><code>6 - Double-precision 32-bit FPU, 64-bit FPU</code><dd>This variant is used by 32-bit ABIs to indicate that the floating-point
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code in the module requires 64-bit wide floating-point registers.
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Double-precision support is used. Only O32 currently supports this
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variant and requires a minimum architecture of MIPS32r2.
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<br><dt><code>7 - Double-precision compat 32-bit FPU, 64-bit FPU</code><dd>This variant is used by 32-bit ABIs to indicate that the floating-point
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code in the module requires 64-bit wide floating-point registers.
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Double-precision support is used. This differs from the previous ABI
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as it restricts use of odd-numbered single-precision registers. Only
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O32 currently supports this variant and requires a minimum architecture
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of MIPS32r2.
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</dl>
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</body></html>
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