106 lines
5.7 KiB
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106 lines
5.7 KiB
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<html lang="en">
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<title>M32R-Warnings - Using as</title>
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<meta name="description" content="Using as">
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="M32R_002dDependent.html#M32R_002dDependent" title="M32R-Dependent">
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<link rel="prev" href="M32R_002dDirectives.html#M32R_002dDirectives" title="M32R-Directives">
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<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage">
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<!--
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This file documents the GNU Assembler "as".
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Copyright (C) 1991-2019 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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Back-Cover Texts. A copy of the license is included in the
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section entitled ``GNU Free Documentation License''.
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</head>
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<body>
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<div class="node">
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<a name="M32R-Warnings"></a>
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<a name="M32R_002dWarnings"></a>
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<p>
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Previous: <a rel="previous" accesskey="p" href="M32R_002dDirectives.html#M32R_002dDirectives">M32R-Directives</a>,
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Up: <a rel="up" accesskey="u" href="M32R_002dDependent.html#M32R_002dDependent">M32R-Dependent</a>
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<hr>
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</div>
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<h4 class="subsection">9.21.3 M32R Warnings</h4>
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<p><a name="index-warnings_002c-M32R-1395"></a><a name="index-M32R-warnings-1396"></a>
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There are several warning and error messages that can be produced by
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<code>as</code> which are specific to the M32R:
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<dl>
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<dt><code>output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?</code><dd>This message is only produced if warnings for explicit parallel
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conflicts have been enabled. It indicates that the assembler has
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encountered a parallel instruction in which the destination register of
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the left hand instruction is used as an input register in the right hand
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instruction. For example in this code fragment
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‘<samp><span class="samp">mv r1, r2 || neg r3, r1</span></samp>’ register r1 is the destination of the
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move instruction and the input to the neg instruction.
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<br><dt><code>output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?</code><dd>This message is only produced if warnings for explicit parallel
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conflicts have been enabled. It indicates that the assembler has
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encountered a parallel instruction in which the destination register of
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the right hand instruction is used as an input register in the left hand
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instruction. For example in this code fragment
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‘<samp><span class="samp">mv r1, r2 || neg r2, r3</span></samp>’ register r2 is the destination of the
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neg instruction and the input to the move instruction.
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<br><dt><code>instruction ‘</code><samp><span class="samp">...</span></samp><code>’ is for the M32RX only</code><dd>This message is produced when the assembler encounters an instruction
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which is only supported by the M32Rx processor, and the ‘<samp><span class="samp">-m32rx</span></samp>’
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command-line flag has not been specified to allow assembly of such
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instructions.
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<br><dt><code>unknown instruction ‘</code><samp><span class="samp">...</span></samp><code>’</code><dd>This message is produced when the assembler encounters an instruction
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which it does not recognize.
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<br><dt><code>only the NOP instruction can be issued in parallel on the m32r</code><dd>This message is produced when the assembler encounters a parallel
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instruction which does not involve a NOP instruction and the
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‘<samp><span class="samp">-m32rx</span></samp>’ command-line flag has not been specified. Only the M32Rx
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processor is able to execute two instructions in parallel.
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<br><dt><code>instruction ‘</code><samp><span class="samp">...</span></samp><code>’ cannot be executed in parallel.</code><dd>This message is produced when the assembler encounters a parallel
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instruction which is made up of one or two instructions which cannot be
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executed in parallel.
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<br><dt><code>Instructions share the same execution pipeline</code><dd>This message is produced when the assembler encounters a parallel
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instruction whose components both use the same execution pipeline.
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<br><dt><code>Instructions write to the same destination register.</code><dd>This message is produced when the assembler encounters a parallel
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instruction where both components attempt to modify the same register.
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For example these code fragments will produce this message:
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‘<samp><span class="samp">mv r1, r2 || neg r1, r3</span></samp>’
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‘<samp><span class="samp">jl r0 || mv r14, r1</span></samp>’
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‘<samp><span class="samp">st r2, @-r1 || mv r1, r3</span></samp>’
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‘<samp><span class="samp">mv r1, r2 || ld r0, @r1+</span></samp>’
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‘<samp><span class="samp">cmp r1, r2 || addx r3, r4</span></samp>’ (Both write to the condition bit)
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</dl>
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<!-- Copyright (C) 1991-2019 Free Software Foundation, Inc. -->
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<!-- This is part of the GAS manual. -->
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<!-- For copying conditions, see the file as.texinfo. -->
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</body></html>
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