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<h4 class="subsection">9.41.1 Options</h4>
<p><a name="index-options-for-s390-2051"></a><a name="index-s390-options-2052"></a>
The following table lists all available s390 specific options:
<a name="index-g_t_0040samp_007b_002dm31_007d-option_002c-s390-2053"></a>
<a name="index-g_t_0040samp_007b_002dm64_007d-option_002c-s390-2054"></a>
<dl><dt><code>-m31 | -m64</code><dd>Select 31- or 64-bit ABI implying a word size of 32- or 64-bit.
<p>These options are only available with the ELF object file format, and
require that the necessary BFD support has been included (on a 31-bit
platform you must add &ndash;enable-64-bit-bfd on the call to the configure
script to enable 64-bit usage and use s390x as target platform).
<p><a name="index-g_t_0040samp_007b_002dmesa_007d-option_002c-s390-2055"></a><a name="index-g_t_0040samp_007b_002dmzarch_007d-option_002c-s390-2056"></a><br><dt><code>-mesa | -mzarch</code><dd>Select the architecture mode, either the Enterprise System Architecture
(esa) mode or the z/Architecture mode (zarch).
<p>The 64-bit instructions are only available with the z/Architecture mode.
The combination of &lsquo;<samp><span class="samp">-m64</span></samp>&rsquo; and &lsquo;<samp><span class="samp">-mesa</span></samp>&rsquo; results in a warning
message.
<p><a name="index-g_t_0040samp_007b_002dmarch_003d_007d-option_002c-s390-2057"></a><br><dt><code>-march=</code><var>CPU</var><dd>This option specifies the target processor. The following processor names
are recognized:
<code>g5</code> (or <code>arch3</code>),
<code>g6</code>,
<code>z900</code> (or <code>arch5</code>),
<code>z990</code> (or <code>arch6</code>),
<code>z9-109</code>,
<code>z9-ec</code> (or <code>arch7</code>),
<code>z10</code> (or <code>arch8</code>),
<code>z196</code> (or <code>arch9</code>),
<code>zEC12</code> (or <code>arch10</code>),
<code>z13</code> (or <code>arch11</code>),
<code>z14</code> (or <code>arch12</code>), and
<code>arch13</code>).
<p>Assembling an instruction that is not supported on the target
processor results in an error message.
<p>The processor names starting with <code>arch</code> refer to the edition
number in the Principle of Operations manual. They can be used as
alternate processor names and have been added for compatibility with
the IBM XL compiler.
<p><code>arch3</code>, <code>g5</code> and <code>g6</code> cannot be used with the
&lsquo;<samp><span class="samp">-mzarch</span></samp>&rsquo; option since the z/Architecture mode is not supported
on these processor levels.
<p>There is no <code>arch4</code> option supported. <code>arch4</code> matches
<code>-march=arch5 -mesa</code>.
<p><a name="index-g_t_0040samp_007b_002dmregnames_007d-option_002c-s390-2058"></a><br><dt><code>-mregnames</code><dd>Allow symbolic names for registers.
<p><a name="index-g_t_0040samp_007b_002dmno_002dregnames_007d-option_002c-s390-2059"></a><br><dt><code>-mno-regnames</code><dd>Do not allow symbolic names for registers.
<p><a name="index-g_t_0040samp_007b_002dmwarn_002dareg_002dzero_007d-option_002c-s390-2060"></a><br><dt><code>-mwarn-areg-zero</code><dd>Warn whenever the operand for a base or index register has been specified
but evaluates to zero. This can indicate the misuse of general purpose
register 0 as an address register.
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