108 lines
3.8 KiB
HTML
108 lines
3.8 KiB
HTML
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<html lang="en">
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<head>
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<title>Sparc-Size-Translations - Using as</title>
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<meta name="description" content="Using as">
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="Sparc_002dSyntax.html#Sparc_002dSyntax" title="Sparc-Syntax">
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<link rel="prev" href="Sparc_002dRelocs.html#Sparc_002dRelocs" title="Sparc-Relocs">
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<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage">
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<!--
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This file documents the GNU Assembler "as".
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Copyright (C) 1991-2019 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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Back-Cover Texts. A copy of the license is included in the
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section entitled ``GNU Free Documentation License''.
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</head>
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<body>
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<div class="node">
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<a name="Sparc-Size-Translations"></a>
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<a name="Sparc_002dSize_002dTranslations"></a>
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<p>
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Previous: <a rel="previous" accesskey="p" href="Sparc_002dRelocs.html#Sparc_002dRelocs">Sparc-Relocs</a>,
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Up: <a rel="up" accesskey="u" href="Sparc_002dSyntax.html#Sparc_002dSyntax">Sparc-Syntax</a>
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<hr>
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</div>
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<h5 class="subsubsection">9.44.3.5 Size Translations</h5>
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<p><a name="index-Sparc-size-translations-2180"></a><a name="index-size_002c-translations_002c-Sparc-2181"></a>
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Often it is desirable to write code in an operand size agnostic
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manner. <code>as</code> provides support for this via
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operand size opcode translations. Translations are supported
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for loads, stores, shifts, compare-and-swap atomics, and the
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‘<samp><span class="samp">clr</span></samp>’ synthetic instruction.
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<p>If generating 32-bit code, <code>as</code> will generate the
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32-bit opcode. Whereas if 64-bit code is being generated,
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the 64-bit opcode will be emitted. For example <code>ldn</code>
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will be transformed into <code>ld</code> for 32-bit code and
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<code>ldx</code> for 64-bit code.
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<p>Here is an example meant to demonstrate all the supported
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opcode translations:
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<pre class="example"> ldn [%o0], %o1
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ldna [%o0] %asi, %o2
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stn %o1, [%o0]
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stna %o2, [%o0] %asi
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slln %o3, 3, %o3
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srln %o4, 8, %o4
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sran %o5, 12, %o5
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casn [%o0], %o1, %o2
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casna [%o0] %asi, %o1, %o2
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clrn %g1
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</pre>
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<p>In 32-bit mode <code>as</code> will emit:
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<pre class="example"> ld [%o0], %o1
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lda [%o0] %asi, %o2
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st %o1, [%o0]
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sta %o2, [%o0] %asi
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sll %o3, 3, %o3
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srl %o4, 8, %o4
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sra %o5, 12, %o5
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cas [%o0], %o1, %o2
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casa [%o0] %asi, %o1, %o2
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clr %g1
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</pre>
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<p>And in 64-bit mode <code>as</code> will emit:
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<pre class="example"> ldx [%o0], %o1
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ldxa [%o0] %asi, %o2
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stx %o1, [%o0]
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stxa %o2, [%o0] %asi
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sllx %o3, 3, %o3
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srlx %o4, 8, %o4
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srax %o5, 12, %o5
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casx [%o0], %o1, %o2
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casxa [%o0] %asi, %o1, %o2
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clrx %g1
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</pre>
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<p>Finally, the ‘<samp><span class="samp">.nword</span></samp>’ translating directive is supported
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as well. It is documented in the section on Sparc machine
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directives.
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</body></html>
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