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231 lines
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<title>RISC-V-Formats - Using as</title>
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="RISC_002dV_002dDependent.html#RISC_002dV_002dDependent" title="RISC-V-Dependent">
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<link rel="prev" href="RISC_002dV_002dDirectives.html#RISC_002dV_002dDirectives" title="RISC-V-Directives">
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<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage">
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<!--
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This file documents the GNU Assembler "as".
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Copyright (C) 1991-2019 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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Back-Cover Texts. A copy of the license is included in the
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<div class="node">
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<a name="RISC-V-Formats"></a>
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<a name="RISC_002dV_002dFormats"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="RISC_002dV_002dATTRIBUTE.html#RISC_002dV_002dATTRIBUTE">RISC-V-ATTRIBUTE</a>,
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Previous: <a rel="previous" accesskey="p" href="RISC_002dV_002dDirectives.html#RISC_002dV_002dDirectives">RISC-V-Directives</a>,
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Up: <a rel="up" accesskey="u" href="RISC_002dV_002dDependent.html#RISC_002dV_002dDependent">RISC-V-Dependent</a>
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<hr>
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</div>
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<h4 class="subsection">9.38.3 Instruction Formats</h4>
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<p><a name="index-instruction-formats_002c-risc_002dv-1999"></a><a name="index-RISC_002dV-instruction-formats-2000"></a>
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The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 12
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instruction formats where some of the formats have multiple variants.
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For the ‘<samp><span class="samp">.insn</span></samp>’ pseudo directive the assembler recognizes some
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of the formats.
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Typically, the most general variant of the instruction format is used
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by the ‘<samp><span class="samp">.insn</span></samp>’ directive.
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<p>The following table lists the abbreviations used in the table of
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instruction formats:
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<pre class="display">
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<p><table summary=""><tr align="left"><td valign="top" width="15%">opcode </td><td valign="top" width="40%">Unsigned immediate or opcode name for 7-bits opcode.
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<br></td></tr><tr align="left"><td valign="top" width="15%">opcode2 </td><td valign="top" width="40%">Unsigned immediate or opcode name for 2-bits opcode.
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<br></td></tr><tr align="left"><td valign="top" width="15%">func7 </td><td valign="top" width="40%">Unsigned immediate for 7-bits function code.
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<br></td></tr><tr align="left"><td valign="top" width="15%">func6 </td><td valign="top" width="40%">Unsigned immediate for 6-bits function code.
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<br></td></tr><tr align="left"><td valign="top" width="15%">func4 </td><td valign="top" width="40%">Unsigned immediate for 4-bits function code.
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<br></td></tr><tr align="left"><td valign="top" width="15%">func3 </td><td valign="top" width="40%">Unsigned immediate for 3-bits function code.
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<br></td></tr><tr align="left"><td valign="top" width="15%">func2 </td><td valign="top" width="40%">Unsigned immediate for 2-bits function code.
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<br></td></tr><tr align="left"><td valign="top" width="15%">rd </td><td valign="top" width="40%">Destination register number for operand x, can be GPR or FPR.
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<br></td></tr><tr align="left"><td valign="top" width="15%">rd' </td><td valign="top" width="40%">Destination register number for operand x,
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only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
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<br></td></tr><tr align="left"><td valign="top" width="15%">rs1 </td><td valign="top" width="40%">First source register number for operand x, can be GPR or FPR.
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<br></td></tr><tr align="left"><td valign="top" width="15%">rs1' </td><td valign="top" width="40%">First source register number for operand x,
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only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
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<br></td></tr><tr align="left"><td valign="top" width="15%">rs2 </td><td valign="top" width="40%">Second source register number for operand x, can be GPR or FPR.
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<br></td></tr><tr align="left"><td valign="top" width="15%">rs2' </td><td valign="top" width="40%">Second source register number for operand x,
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only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
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<br></td></tr><tr align="left"><td valign="top" width="15%">simm12 </td><td valign="top" width="40%">Sign-extended 12-bit immediate for operand x.
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<br></td></tr><tr align="left"><td valign="top" width="15%">simm20 </td><td valign="top" width="40%">Sign-extended 20-bit immediate for operand x.
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<br></td></tr><tr align="left"><td valign="top" width="15%">simm6 </td><td valign="top" width="40%">Sign-extended 6-bit immediate for operand x.
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<br></td></tr><tr align="left"><td valign="top" width="15%">uimm8 </td><td valign="top" width="40%">Unsigned 8-bit immediate for operand x.
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<br></td></tr><tr align="left"><td valign="top" width="15%">symbol </td><td valign="top" width="40%">Symbol or lable reference for operand x.
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<br></td></tr></table>
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</pre>
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<p>The following table lists all available opcode name:
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<dl>
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<dt><code>C0</code><br><dt><code>C1</code><br><dt><code>C2</code><dd>Opcode space for compressed instructions.
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<br><dt><code>LOAD</code><dd>Opcode space for load instructions.
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<br><dt><code>LOAD_FP</code><dd>Opcode space for floating-point load instructions.
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<br><dt><code>STORE</code><dd>Opcode space for store instructions.
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<br><dt><code>STORE_FP</code><dd>Opcode space for floating-point store instructions.
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<br><dt><code>AUIPC</code><dd>Opcode space for auipc instruction.
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<br><dt><code>LUI</code><dd>Opcode space for lui instruction.
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<br><dt><code>BRANCH</code><dd>Opcode space for branch instructions.
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<br><dt><code>JAL</code><dd>Opcode space for jal instruction.
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<br><dt><code>JALR</code><dd>Opcode space for jalr instruction.
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<br><dt><code>OP</code><dd>Opcode space for ALU instructions.
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<br><dt><code>OP_32</code><dd>Opcode space for 32-bits ALU instructions.
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<br><dt><code>OP_IMM</code><dd>Opcode space for ALU with immediate instructions.
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<br><dt><code>OP_IMM_32</code><dd>Opcode space for 32-bits ALU with immediate instructions.
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<br><dt><code>OP_FP</code><dd>Opcode space for floating-point operation instructions.
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<br><dt><code>MADD</code><dd>Opcode space for madd instruction.
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<br><dt><code>MSUB</code><dd>Opcode space for msub instruction.
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<br><dt><code>NMADD</code><dd>Opcode space for nmadd instruction.
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<br><dt><code>NMSUB</code><dd>Opcode space for msub instruction.
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<br><dt><code>AMO</code><dd>Opcode space for atomic memory operation instructions.
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<br><dt><code>MISC_MEM</code><dd>Opcode space for misc instructions.
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<br><dt><code>SYSTEM</code><dd>Opcode space for system instructions.
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<br><dt><code>CUSTOM_0</code><br><dt><code>CUSTOM_1</code><br><dt><code>CUSTOM_2</code><br><dt><code>CUSTOM_3</code><dd>Opcode space for customize instructions.
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</dl>
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<p>An instruction is two or four bytes in length and must be aligned
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on a 2 byte boundary. The first two bits of the instruction specify the
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length of the instruction, 00, 01 and 10 indicates a two byte instruction,
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11 indicates a four byte instruction.
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<p>The following table lists the RISC-V instruction formats that are available
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with the ‘<samp><span class="samp">.insn</span></samp>’ pseudo directive:
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<dl>
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<dt><code>R type: .insn r opcode, func3, func7, rd, rs1, rs2</code><dd><pre class="verbatim"> +-------+-----+-----+-------+----+-------------+
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| func7 | rs2 | rs1 | func3 | rd | opcode |
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+-------+-----+-----+-------+----+-------------+
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31 25 20 15 12 7 0
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</pre>
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<br><dt><code>R type with 4 register operands: .insn r opcode, func3, func2, rd, rs1, rs2, rs3</code><dt><code>R4 type: .insn r4 opcode, func3, func2, rd, rs1, rs2, rs3</code><dd><pre class="verbatim"> +-----+-------+-----+-----+-------+----+-------------+
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| rs3 | func2 | rs2 | rs1 | func3 | rd | opcode |
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+-----+-------+-----+-----+-------+----+-------------+
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31 27 25 20 15 12 7 0
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</pre>
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<br><dt><code>I type: .insn i opcode, func3, rd, rs1, simm12</code><dd><pre class="verbatim"> +-------------+-----+-------+----+-------------+
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| simm12 | rs1 | func3 | rd | opcode |
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+-------------+-----+-------+----+-------------+
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31 20 15 12 7 0
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</pre>
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<br><dt><code>S type: .insn s opcode, func3, rd, rs1, simm12</code><dd><pre class="verbatim"> +--------------+-----+-----+-------+-------------+-------------+
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| simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode |
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+--------------+-----+-----+-------+-------------+-------------+
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31 25 20 15 12 7 0
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</pre>
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<br><dt><code>SB type: .insn sb opcode, func3, rd, rs1, symbol</code><dt><code>SB type: .insn sb opcode, func3, rd, simm12(rs1)</code><dt><code>B type: .insn s opcode, func3, rd, rs1, symbol</code><dt><code>B type: .insn s opcode, func3, rd, simm12(rs1)</code><dd><pre class="verbatim"> +------------+--------------+-----+-----+-------+-------------+-------------+--------+
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| simm12[12] | simm12[10:5] | rs2 | rs1 | func3 | simm12[4:1] | simm12[11]] | opcode |
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+------------+--------------+-----+-----+-------+-------------+-------------+--------+
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31 30 25 20 15 12 7 0
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</pre>
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<br><dt><code>U type: .insn u opcode, rd, simm20</code><dd><pre class="verbatim"> +---------------------------+----+-------------+
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| simm20 | rd | opcode |
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+---------------------------+----+-------------+
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31 12 7 0
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</pre>
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<br><dt><code>UJ type: .insn uj opcode, rd, symbol</code><dt><code>J type: .insn j opcode, rd, symbol</code><dd><pre class="verbatim"> +------------+--------------+------------+---------------+----+-------------+
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| simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode |
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+------------+--------------+------------+---------------+----+-------------+
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31 30 21 20 12 7 0
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</pre>
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<br><dt><code>CR type: .insn cr opcode2, func4, rd, rs2</code><dd><pre class="verbatim"> +---------+--------+-----+---------+
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| func4 | rd/rs1 | rs2 | opcode2 |
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+---------+--------+-----+---------+
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15 12 7 2 0
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</pre>
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<br><dt><code>CI type: .insn ci opcode2, func3, rd, simm6</code><dd><pre class="verbatim"> +---------+-----+--------+-----+---------+
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| func3 | imm | rd/rs1 | imm | opcode2 |
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+---------+-----+--------+-----+---------+
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15 13 12 7 2 0
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</pre>
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<br><dt><code>CIW type: .insn ciw opcode2, func3, rd, uimm8</code><dd><pre class="verbatim"> +---------+--------------+-----+---------+
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| func3 | imm | rd' | opcode2 |
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+---------+--------------+-----+---------+
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15 13 7 2 0
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</pre>
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<br><dt><code>CA type: .insn ca opcode2, func6, func2, rd, rs2</code><dd><pre class="verbatim"> +---------+----------+-------+------+--------+
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| func6 | rd'/rs1' | func2 | rs2' | opcode |
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+---------+----------+-------+------+--------+
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15 10 7 5 2 0
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</pre>
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<br><dt><code>CB type: .insn cb opcode2, func3, rs1, symbol</code><dd><pre class="verbatim"> +---------+--------+------+--------+---------+
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| func3 | offset | rs1' | offset | opcode2 |
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+---------+--------+------+--------+---------+
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15 13 10 7 2 0
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</pre>
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<br><dt><code>CJ type: .insn cj opcode2, symbol</code><dd><pre class="verbatim"> +---------+--------------------+---------+
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| func3 | jump target | opcode2 |
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+---------+--------------------+---------+
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15 13 7 2 0
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</pre>
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</dl>
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<p>For the complete list of all instruction format variants see
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The RISC-V Instruction Set Manual Volume I: User-Level ISA.
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</body></html>
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