164 lines
6.8 KiB
HTML
164 lines
6.8 KiB
HTML
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<html lang="en">
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<head>
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<title>PowerPC-Opts - Using as</title>
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<meta name="description" content="Using as">
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<meta name="generator" content="makeinfo 4.13">
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="PPC_002dDependent.html#PPC_002dDependent" title="PPC-Dependent">
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<link rel="next" href="PowerPC_002dPseudo.html#PowerPC_002dPseudo" title="PowerPC-Pseudo">
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<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage">
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<!--
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This file documents the GNU Assembler "as".
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Copyright (C) 1991-2019 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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Back-Cover Texts. A copy of the license is included in the
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section entitled ``GNU Free Documentation License''.
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-->
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<style type="text/css"><!--
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--></style>
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</head>
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<body>
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<div class="node">
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<a name="PowerPC-Opts"></a>
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<a name="PowerPC_002dOpts"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="PowerPC_002dPseudo.html#PowerPC_002dPseudo">PowerPC-Pseudo</a>,
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Up: <a rel="up" accesskey="u" href="PPC_002dDependent.html#PPC_002dDependent">PPC-Dependent</a>
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<hr>
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</div>
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<h4 class="subsection">9.36.1 Options</h4>
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<p><a name="index-options-for-PowerPC-1947"></a><a name="index-PowerPC-options-1948"></a><a name="index-architectures_002c-PowerPC-1949"></a><a name="index-PowerPC-architectures-1950"></a>The PowerPC chip family includes several successive levels, using the same
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core instruction set, but including a few additional instructions at
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each level. There are exceptions to this however. For details on what
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instructions each variant supports, please see the chip's architecture
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reference manual.
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<p>The following table lists all available PowerPC options.
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<!-- man begin OPTIONS -->
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<dl>
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<dt><code>-a32</code><dd>Generate ELF32 or XCOFF32.
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<br><dt><code>-a64</code><dd>Generate ELF64 or XCOFF64.
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<br><dt><code>-K PIC</code><dd>Set EF_PPC_RELOCATABLE_LIB in ELF flags.
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<br><dt><code>-mpwrx | -mpwr2</code><dd>Generate code for POWER/2 (RIOS2).
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<br><dt><code>-mpwr</code><dd>Generate code for POWER (RIOS1)
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<br><dt><code>-m601</code><dd>Generate code for PowerPC 601.
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<br><dt><code>-mppc, -mppc32, -m603, -m604</code><dd>Generate code for PowerPC 603/604.
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<br><dt><code>-m403, -m405</code><dd>Generate code for PowerPC 403/405.
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<br><dt><code>-m440</code><dd>Generate code for PowerPC 440. BookE and some 405 instructions.
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<br><dt><code>-m464</code><dd>Generate code for PowerPC 464.
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<br><dt><code>-m476</code><dd>Generate code for PowerPC 476.
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<br><dt><code>-m7400, -m7410, -m7450, -m7455</code><dd>Generate code for PowerPC 7400/7410/7450/7455.
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<br><dt><code>-m750cl, -mgekko, -mbroadway</code><dd>Generate code for PowerPC 750CL/Gekko/Broadway.
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<br><dt><code>-m821, -m850, -m860</code><dd>Generate code for PowerPC 821/850/860.
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<br><dt><code>-mppc64, -m620</code><dd>Generate code for PowerPC 620/625/630.
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<br><dt><code>-me500, -me500x2</code><dd>Generate code for Motorola e500 core complex.
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<br><dt><code>-me500mc</code><dd>Generate code for Freescale e500mc core complex.
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<br><dt><code>-me500mc64</code><dd>Generate code for Freescale e500mc64 core complex.
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<br><dt><code>-me5500</code><dd>Generate code for Freescale e5500 core complex.
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<br><dt><code>-me6500</code><dd>Generate code for Freescale e6500 core complex.
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<br><dt><code>-mspe</code><dd>Generate code for Motorola SPE instructions.
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<br><dt><code>-mspe2</code><dd>Generate code for Freescale SPE2 instructions.
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<br><dt><code>-mtitan</code><dd>Generate code for AppliedMicro Titan core complex.
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<br><dt><code>-mppc64bridge</code><dd>Generate code for PowerPC 64, including bridge insns.
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<br><dt><code>-mbooke</code><dd>Generate code for 32-bit BookE.
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<br><dt><code>-ma2</code><dd>Generate code for A2 architecture.
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<br><dt><code>-me300</code><dd>Generate code for PowerPC e300 family.
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<br><dt><code>-maltivec</code><dd>Generate code for processors with AltiVec instructions.
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<br><dt><code>-mvle</code><dd>Generate code for Freescale PowerPC VLE instructions.
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<br><dt><code>-mvsx</code><dd>Generate code for processors with Vector-Scalar (VSX) instructions.
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<br><dt><code>-mhtm</code><dd>Generate code for processors with Hardware Transactional Memory instructions.
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<br><dt><code>-mpower4, -mpwr4</code><dd>Generate code for Power4 architecture.
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<br><dt><code>-mpower5, -mpwr5, -mpwr5x</code><dd>Generate code for Power5 architecture.
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<br><dt><code>-mpower6, -mpwr6</code><dd>Generate code for Power6 architecture.
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<br><dt><code>-mpower7, -mpwr7</code><dd>Generate code for Power7 architecture.
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<br><dt><code>-mpower8, -mpwr8</code><dd>Generate code for Power8 architecture.
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<br><dt><code>-mpower9, -mpwr9</code><dd>Generate code for Power9 architecture.
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<br><dt><code>-mcell</code><br><dt><code>-mcell</code><dd>Generate code for Cell Broadband Engine architecture.
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<br><dt><code>-mcom</code><dd>Generate code Power/PowerPC common instructions.
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<br><dt><code>-many</code><dd>Generate code for any architecture (PWR/PWRX/PPC).
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<br><dt><code>-mregnames</code><dd>Allow symbolic names for registers.
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<br><dt><code>-mno-regnames</code><dd>Do not allow symbolic names for registers.
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<br><dt><code>-mrelocatable</code><dd>Support for GCC's -mrelocatable option.
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<br><dt><code>-mrelocatable-lib</code><dd>Support for GCC's -mrelocatable-lib option.
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<br><dt><code>-memb</code><dd>Set PPC_EMB bit in ELF flags.
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<br><dt><code>-mlittle, -mlittle-endian, -le</code><dd>Generate code for a little endian machine.
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<br><dt><code>-mbig, -mbig-endian, -be</code><dd>Generate code for a big endian machine.
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<br><dt><code>-msolaris</code><dd>Generate code for Solaris.
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<br><dt><code>-mno-solaris</code><dd>Do not generate code for Solaris.
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<br><dt><code>-nops=</code><var>count</var><dd>If an alignment directive inserts more than <var>count</var> nops, put a
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branch at the beginning to skip execution of the nops.
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</dl>
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<!-- man end -->
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</body></html>
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