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280 lines
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<title>ARC Directives - Using as</title>
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<meta name="description" content="Using as">
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<link title="Top" rel="start" href="index.html#Top">
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<link rel="up" href="ARC_002dDependent.html#ARC_002dDependent" title="ARC-Dependent">
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<link rel="prev" href="ARC-Syntax.html#ARC-Syntax" title="ARC Syntax">
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<link rel="next" href="ARC-Modifiers.html#ARC-Modifiers" title="ARC Modifiers">
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<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage">
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<!--
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This file documents the GNU Assembler "as".
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Copyright (C) 1991-2019 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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under the terms of the GNU Free Documentation License, Version 1.3
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or any later version published by the Free Software Foundation;
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with no Invariant Sections, with no Front-Cover Texts, and with no
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Back-Cover Texts. A copy of the license is included in the
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section entitled ``GNU Free Documentation License''.
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</head>
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<body>
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<div class="node">
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<a name="ARC-Directives"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="ARC-Modifiers.html#ARC-Modifiers">ARC Modifiers</a>,
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Previous: <a rel="previous" accesskey="p" href="ARC-Syntax.html#ARC-Syntax">ARC Syntax</a>,
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Up: <a rel="up" accesskey="u" href="ARC_002dDependent.html#ARC_002dDependent">ARC-Dependent</a>
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<hr>
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</div>
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<h4 class="subsection">9.3.3 ARC Machine Directives</h4>
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<p><a name="index-machine-directives_002c-ARC-704"></a><a name="index-ARC-machine-directives-705"></a>The ARC version of <code>as</code> supports the following additional
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machine directives:
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<a name="index-g_t_0040code_007blcomm_007d-directive-706"></a>
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<dl><dt><code>.lcomm </code><var>symbol</var><code>, </code><var>length</var><code>[, </code><var>alignment</var><code>]</code><dd>Reserve <var>length</var> (an absolute expression) bytes for a local common
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denoted by <var>symbol</var>. The section and value of <var>symbol</var> are
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those of the new local common. The addresses are allocated in the bss
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section, so that at run-time the bytes start off zeroed. Since
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<var>symbol</var> is not declared global, it is normally not visible to
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<code>ld</code>. The optional third parameter, <var>alignment</var>,
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specifies the desired alignment of the symbol in the bss section,
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specified as a byte boundary (for example, an alignment of 16 means
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that the least significant 4 bits of the address should be zero). The
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alignment must be an absolute expression, and it must be a power of
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two. If no alignment is specified, as will set the alignment to the
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largest power of two less than or equal to the size of the symbol, up
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to a maximum of 16.
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<p><a name="index-g_t_0040code_007blcommon_007d-directive_002c-ARC-707"></a><br><dt><code>.lcommon </code><var>symbol</var><code>, </code><var>length</var><code>[, </code><var>alignment</var><code>]</code><dd>The same as <code>lcomm</code> directive.
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<p><a name="index-g_t_0040code_007bcpu_007d-directive_002c-ARC-708"></a><br><dt><code>.cpu </code><var>cpu</var><dd>The <code>.cpu</code> directive must be followed by the desired core
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version. Permitted values for CPU are:
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<dl>
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<dt><code>ARC600</code><dd>Assemble for the ARC600 instruction set.
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<br><dt><code>arc600_norm</code><dd>Assemble for ARC 600 with norm instructions.
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<br><dt><code>arc600_mul64</code><dd>Assemble for ARC 600 with mul64 instructions.
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<br><dt><code>arc600_mul32x16</code><dd>Assemble for ARC 600 with mul32x16 instructions.
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<br><dt><code>arc601</code><dd>Assemble for ARC 601 instruction set.
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<br><dt><code>arc601_norm</code><dd>Assemble for ARC 601 with norm instructions.
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<br><dt><code>arc601_mul64</code><dd>Assemble for ARC 601 with mul64 instructions.
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<br><dt><code>arc601_mul32x16</code><dd>Assemble for ARC 601 with mul32x16 instructions.
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<br><dt><code>ARC700</code><dd>Assemble for the ARC700 instruction set.
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<br><dt><code>NPS400</code><dd>Assemble for the NPS400 instruction set.
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<br><dt><code>EM</code><dd>Assemble for the ARC EM instruction set.
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<br><dt><code>arcem</code><dd>Assemble for ARC EM instruction set
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<br><dt><code>em4</code><dd>Assemble for ARC EM with code-density instructions.
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<br><dt><code>em4_dmips</code><dd>Assemble for ARC EM with code-density instructions.
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<br><dt><code>em4_fpus</code><dd>Assemble for ARC EM with code-density instructions.
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<br><dt><code>em4_fpuda</code><dd>Assemble for ARC EM with code-density, and double-precision assist
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instructions.
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<br><dt><code>quarkse_em</code><dd>Assemble for QuarkSE-EM instruction set.
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<br><dt><code>HS</code><dd>Assemble for the ARC HS instruction set.
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<br><dt><code>archs</code><dd>Assemble for ARC HS instruction set.
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<br><dt><code>hs</code><dd>Assemble for ARC HS instruction set.
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<br><dt><code>hs34</code><dd>Assemble for ARC HS34 instruction set.
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<br><dt><code>hs38</code><dd>Assemble for ARC HS38 instruction set.
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<br><dt><code>hs38_linux</code><dd>Assemble for ARC HS38 with floating point support on.
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</dl>
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<p>Note: the <code>.cpu</code> directive overrides the command-line option
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<code>-mcpu=</code><var>cpu</var>; a warning is emitted when the version is not
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consistent between the two.
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<br><dt><code>.extAuxRegister </code><var>name</var><code>, </code><var>addr</var><code>, </code><var>mode</var><dd><a name="index-g_t_0040code_007bextAuxRegister_007d-directive_002c-ARC-709"></a>Auxiliary registers can be defined in the assembler source code by
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using this directive. The first parameter, <var>name</var>, is the name of the
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new auxiliary register. The second parameter, <var>addr</var>, is
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address the of the auxiliary register. The third parameter,
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<var>mode</var>, specifies whether the register is readable and/or writable
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and is one of:
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<dl>
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<dt><code>r</code><dd>Read only;
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<br><dt><code>w</code><dd>Write only;
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<br><dt><code>r|w</code><dd>Read and write.
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</dl>
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<p>For example:
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<pre class="example"> .extAuxRegister mulhi, 0x12, w
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</pre>
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<p>specifies a write only extension auxiliary register, <var>mulhi</var> at
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address 0x12.
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<br><dt><code>.extCondCode </code><var>suffix</var><code>, </code><var>val</var><dd><a name="index-g_t_0040code_007bextCondCode_007d-directive_002c-ARC-710"></a>ARC supports extensible condition codes. This directive defines a new
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condition code, to be known by the suffix, <var>suffix</var> and will
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depend on the value, <var>val</var> in the condition code.
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<p>For example:
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<pre class="example"> .extCondCode is_busy,0x14
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add.is_busy r1,r2,r3
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</pre>
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<p>will only execute the <code>add</code> instruction if the condition code
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value is 0x14.
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<br><dt><code>.extCoreRegister </code><var>name</var><code>, </code><var>regnum</var><code>, </code><var>mode</var><code>, </code><var>shortcut</var><dd><a name="index-g_t_0040code_007bextCoreRegister_007d-directive_002c-ARC-711"></a>Specifies an extension core register named <var>name</var> as a synonym for
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the register numbered <var>regnum</var>. The register number must be
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between 32 and 59. The third argument, <var>mode</var>, indicates whether
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the register is readable and/or writable and is one of:
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<dl>
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<dt><code>r</code><dd>Read only;
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<br><dt><code>w</code><dd>Write only;
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<br><dt><code>r|w</code><dd>Read and write.
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</dl>
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<p>The final parameter, <var>shortcut</var> indicates whether the register has
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a short cut in the pipeline. The valid values are:
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<dl>
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<dt><code>can_shortcut</code><dd>The register has a short cut in the pipeline;
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<br><dt><code>cannot_shortcut</code><dd>The register does not have a short cut in the pipeline.
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</dl>
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<p>For example:
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<pre class="example"> .extCoreRegister mlo, 57, r , can_shortcut
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</pre>
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<p>defines a read only extension core register, <code>mlo</code>, which is
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register 57, and can short cut the pipeline.
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<br><dt><code>.extInstruction </code><var>name</var><code>, </code><var>opcode</var><code>, </code><var>subopcode</var><code>, </code><var>suffixclass</var><code>, </code><var>syntaxclass</var><dd><a name="index-g_t_0040code_007bextInstruction_007d-directive_002c-ARC-712"></a>ARC allows the user to specify extension instructions. These
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extension instructions are not macros; the assembler creates encodings
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for use of these instructions according to the specification by the
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user.
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<p>The first argument, <var>name</var>, gives the name of the instruction.
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<p>The second argument, <var>opcode</var>, is the opcode to be used (bits 31:27
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in the encoding).
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<p>The third argument, <var>subopcode</var>, is the sub-opcode to be used, but
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the correct value also depends on the fifth argument,
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<var>syntaxclass</var>
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<p>The fourth argument, <var>suffixclass</var>, determines the kinds of
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suffixes to be allowed. Valid values are:
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<dl>
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<dt><code>SUFFIX_NONE</code><dd>No suffixes are permitted;
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<br><dt><code>SUFFIX_COND</code><dd>Conditional suffixes are permitted;
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<br><dt><code>SUFFIX_FLAG</code><dd>Flag setting suffixes are permitted.
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<br><dt><code>SUFFIX_COND|SUFFIX_FLAG</code><dd>Both conditional and flag setting suffices are permitted.
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</dl>
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<p>The fifth and final argument, <var>syntaxclass</var>, determines the syntax
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class for the instruction. It can have the following values:
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<dl>
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<dt><code>SYNTAX_2OP</code><dd>Two Operand Instruction;
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<br><dt><code>SYNTAX_3OP</code><dd>Three Operand Instruction.
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<br><dt><code>SYNTAX_1OP</code><dd>One Operand Instruction.
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<br><dt><code>SYNTAX_NOP</code><dd>No Operand Instruction.
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</dl>
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<p>The syntax class may be followed by ‘<samp><span class="samp">|</span></samp>’ and one of the following
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modifiers.
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<dl>
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<dt><code>OP1_MUST_BE_IMM</code><dd>Modifies syntax class <code>SYNTAX_3OP</code>, specifying that the first
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operand of a three-operand instruction must be an immediate (i.e., the
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result is discarded). This is usually used to set the flags using
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specific instructions and not retain results.
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<br><dt><code>OP1_IMM_IMPLIED</code><dd>Modifies syntax class <code>SYNTAX_20P</code>, specifying that there is an
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implied immediate destination operand which does not appear in the
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syntax.
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<p>For example, if the source code contains an instruction like:
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<pre class="example"> inst r1,r2
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</pre>
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<p>the first argument is an implied immediate (that is, the result is
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discarded). This is the same as though the source code were: inst
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0,r1,r2.
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</dl>
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<p>For example, defining a 64-bit multiplier with immediate operands:
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<pre class="example"> .extInstruction mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG,
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SYNTAX_3OP|OP1_MUST_BE_IMM
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</pre>
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<p>which specifies an extension instruction named <code>mp64</code> with 3
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operands. It sets the flags and can be used with a condition code,
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for which the first operand is an immediate, i.e. equivalent to
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discarding the result of the operation.
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<p>A two operands instruction variant would be:
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<pre class="example"> .extInstruction mul64, 0x07, 0x2d, SUFFIX_COND,
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SYNTAX_2OP|OP1_IMM_IMPLIED
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</pre>
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<p>which describes a two operand instruction with an implicit first
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immediate operand. The result of this operation would be discarded.
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<p><a name="index-g_t_0040code_007b_002earc_005fattribute_007d-directive_002c-ARC-713"></a><br><dt><code>.arc_attribute </code><var>tag</var><code>, </code><var>value</var><dd>Set the ARC object attribute <var>tag</var> to <var>value</var>.
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<p>The <var>tag</var> is either an attribute number, or one of the following:
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<code>Tag_ARC_PCS_config</code>, <code>Tag_ARC_CPU_base</code>,
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<code>Tag_ARC_CPU_variation</code>, <code>Tag_ARC_CPU_name</code>,
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<code>Tag_ARC_ABI_rf16</code>, <code>Tag_ARC_ABI_osver</code>, <code>Tag_ARC_ABI_sda</code>,
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<code>Tag_ARC_ABI_pic</code>, <code>Tag_ARC_ABI_tls</code>, <code>Tag_ARC_ABI_enumsize</code>,
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<code>Tag_ARC_ABI_exceptions</code>, <code>Tag_ARC_ABI_double_size</code>,
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<code>Tag_ARC_ISA_config</code>, <code>Tag_ARC_ISA_apex</code>,
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<code>Tag_ARC_ISA_mpy_option</code>
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<p>The <var>value</var> is either a <code>number</code>, <code>"string"</code>, or
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<code>number, "string"</code> depending on the tag.
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</dl>
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</body></html>
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