597 lines
14 KiB
C
597 lines
14 KiB
C
/*
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* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* Top-level SMC handler for ZynqMP power management calls and
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* IPI setup functions for communication with PMU.
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*/
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#include <errno.h>
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#include <common/runtime_svc.h>
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#if ZYNQMP_WDT_RESTART
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#include <arch_helpers.h>
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#include <drivers/arm/gicv2.h>
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#include <lib/mmio.h>
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#include <lib/spinlock.h>
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#include <plat/common/platform.h>
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#endif
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#include <plat_private.h>
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#include "pm_api_sys.h"
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#include "pm_client.h"
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#include "pm_ipi.h"
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#define PM_SET_SUSPEND_MODE 0xa02
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#define PM_GET_TRUSTZONE_VERSION 0xa03
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/* !0 - UP, 0 - DOWN */
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static int32_t pm_up = 0;
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#if ZYNQMP_WDT_RESTART
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static spinlock_t inc_lock;
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static int active_cores = 0;
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#endif
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/**
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* pm_context - Structure which contains data for power management
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* @api_version version of PM API, must match with one on PMU side
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* @payload payload array used to store received
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* data from ipi buffer registers
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*/
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static struct {
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uint32_t api_version;
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uint32_t payload[PAYLOAD_ARG_CNT];
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} pm_ctx;
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#if ZYNQMP_WDT_RESTART
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/**
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* trigger_wdt_restart() - Trigger warm restart event to APU cores
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*
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* This function triggers SGI for all active APU CPUs. SGI handler then
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* power down CPU and call system reset.
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*/
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static void trigger_wdt_restart(void)
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{
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uint32_t core_count = 0;
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uint32_t core_status[3];
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uint32_t target_cpu_list = 0;
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int i;
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for (i = 0; i < 4; i++) {
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pm_get_node_status(NODE_APU_0 + i, core_status);
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if (core_status[0] == 1) {
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core_count++;
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target_cpu_list |= (1 << i);
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}
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}
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spin_lock(&inc_lock);
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active_cores = core_count;
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spin_unlock(&inc_lock);
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INFO("Active Cores: %d\n", active_cores);
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/* trigger SGI to active cores */
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gicv2_raise_sgi(ARM_IRQ_SEC_SGI_7, target_cpu_list);
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}
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/**
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* ttc_fiq_handler() - TTC Handler for timer event
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* @id number of the highest priority pending interrupt of the type
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* that this handler was registered for
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* @flags security state, bit[0]
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* @handler pointer to 'cpu_context' structure of the current CPU for the
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* security state specified in the 'flags' parameter
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* @cookie unused
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*
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* Function registered as INTR_TYPE_EL3 interrupt handler
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*
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* When WDT event is received in PMU, PMU needs to notify master to do cleanup
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* if required. PMU sets up timer and starts timer to overflow in zero time upon
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* WDT event. ATF handles this timer event and takes necessary action required
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* for warm restart.
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*
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* In presence of non-secure software layers (EL1/2) sets the interrupt
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* at registered entrance in GIC and informs that PMU responsed or demands
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* action.
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*/
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static uint64_t ttc_fiq_handler(uint32_t id, uint32_t flags, void *handle,
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void *cookie)
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{
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INFO("BL31: Got TTC FIQ\n");
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/* Clear TTC interrupt by reading interrupt register */
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mmio_read_32(TTC3_INTR_REGISTER_1);
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/* Disable the timer interrupts */
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mmio_write_32(TTC3_INTR_ENABLE_1, 0);
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trigger_wdt_restart();
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return 0;
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}
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/**
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* zynqmp_sgi7_irq() - Handler for SGI7 IRQ
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* @id number of the highest priority pending interrupt of the type
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* that this handler was registered for
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* @flags security state, bit[0]
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* @handler pointer to 'cpu_context' structure of the current CPU for the
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* security state specified in the 'flags' parameter
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* @cookie unused
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*
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* Function registered as INTR_TYPE_EL3 interrupt handler
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*
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* On receiving WDT event from PMU, ATF generates SGI7 to all running CPUs.
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* In response to SGI7 interrupt, each CPUs do clean up if required and last
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* running CPU calls system restart.
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*/
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static uint64_t __unused __dead2 zynqmp_sgi7_irq(uint32_t id, uint32_t flags,
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void *handle, void *cookie)
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{
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int i;
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/* enter wfi and stay there */
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INFO("Entering wfi\n");
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spin_lock(&inc_lock);
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active_cores--;
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for (i = 0; i < 4; i++) {
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mmio_write_32(BASE_GICD_BASE + GICD_CPENDSGIR + 4 * i,
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0xffffffff);
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}
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spin_unlock(&inc_lock);
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if (active_cores == 0) {
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pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET,
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PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM);
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}
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/* enter wfi and stay there */
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while (1)
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wfi();
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}
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/**
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* pm_wdt_restart_setup() - Setup warm restart interrupts
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*
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* This function sets up handler for SGI7 and TTC interrupts
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* used for warm restart.
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*/
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static int pm_wdt_restart_setup(void)
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{
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int ret;
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/* register IRQ handler for SGI7 */
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ret = request_intr_type_el3(ARM_IRQ_SEC_SGI_7, zynqmp_sgi7_irq);
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if (ret) {
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WARN("BL31: registering SGI7 interrupt failed\n");
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goto err;
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}
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ret = request_intr_type_el3(IRQ_TTC3_1, ttc_fiq_handler);
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if (ret)
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WARN("BL31: registering TTC3 interrupt failed\n");
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err:
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return ret;
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}
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#endif
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/**
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* pm_setup() - PM service setup
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*
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* @return On success, the initialization function must return 0.
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* Any other return value will cause the framework to ignore
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* the service
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*
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* Initialization functions for ZynqMP power management for
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* communicaton with PMU.
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*
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* Called from sip_svc_setup initialization function with the
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* rt_svc_init signature.
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*/
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int pm_setup(void)
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{
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int status, ret;
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status = pm_ipi_init(primary_proc);
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#if ZYNQMP_WDT_RESTART
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status = pm_wdt_restart_setup();
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if (status)
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WARN("BL31: warm-restart setup failed\n");
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#endif
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if (status >= 0) {
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INFO("BL31: PM Service Init Complete: API v%d.%d\n",
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PM_VERSION_MAJOR, PM_VERSION_MINOR);
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ret = 0;
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} else {
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INFO("BL31: PM Service Init Failed, Error Code %d!\n", status);
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ret = status;
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}
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pm_up = !status;
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return ret;
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}
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/**
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* pm_smc_handler() - SMC handler for PM-API calls coming from EL1/EL2.
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* @smc_fid - Function Identifier
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* @x1 - x4 - Arguments
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* @cookie - Unused
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* @handler - Pointer to caller's context structure
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*
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* @return - Unused
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*
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* Determines that smc_fid is valid and supported PM SMC Function ID from the
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* list of pm_api_ids, otherwise completes the request with
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* the unknown SMC Function ID
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*
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* The SMC calls for PM service are forwarded from SIP Service SMC handler
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* function with rt_svc_handle signature
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*/
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uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
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uint64_t x4, void *cookie, void *handle, uint64_t flags)
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{
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enum pm_ret_status ret;
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uint32_t pm_arg[4];
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/* Handle case where PM wasn't initialized properly */
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if (!pm_up)
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SMC_RET1(handle, SMC_UNK);
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pm_arg[0] = (uint32_t)x1;
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pm_arg[1] = (uint32_t)(x1 >> 32);
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pm_arg[2] = (uint32_t)x2;
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pm_arg[3] = (uint32_t)(x2 >> 32);
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switch (smc_fid & FUNCID_NUM_MASK) {
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/* PM API Functions */
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case PM_SELF_SUSPEND:
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ret = pm_self_suspend(pm_arg[0], pm_arg[1], pm_arg[2],
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pm_arg[3]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_REQ_SUSPEND:
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ret = pm_req_suspend(pm_arg[0], pm_arg[1], pm_arg[2],
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pm_arg[3]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_REQ_WAKEUP:
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{
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/* Use address flag is encoded in the 1st bit of the low-word */
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unsigned int set_addr = pm_arg[1] & 0x1;
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uint64_t address = (uint64_t)pm_arg[2] << 32;
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address |= pm_arg[1] & (~0x1);
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ret = pm_req_wakeup(pm_arg[0], set_addr, address,
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pm_arg[3]);
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SMC_RET1(handle, (uint64_t)ret);
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}
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case PM_FORCE_POWERDOWN:
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ret = pm_force_powerdown(pm_arg[0], pm_arg[1]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_ABORT_SUSPEND:
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ret = pm_abort_suspend(pm_arg[0]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_SET_WAKEUP_SOURCE:
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ret = pm_set_wakeup_source(pm_arg[0], pm_arg[1], pm_arg[2]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_SYSTEM_SHUTDOWN:
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ret = pm_system_shutdown(pm_arg[0], pm_arg[1]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_REQ_NODE:
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ret = pm_req_node(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_RELEASE_NODE:
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ret = pm_release_node(pm_arg[0]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_SET_REQUIREMENT:
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ret = pm_set_requirement(pm_arg[0], pm_arg[1], pm_arg[2],
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pm_arg[3]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_SET_MAX_LATENCY:
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ret = pm_set_max_latency(pm_arg[0], pm_arg[1]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_GET_API_VERSION:
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/* Check is PM API version already verified */
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if (pm_ctx.api_version == PM_VERSION) {
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SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS |
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((uint64_t)PM_VERSION << 32));
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}
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ret = pm_get_api_version(&pm_ctx.api_version);
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/*
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* Enable IPI IRQ
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* assume the rich OS is OK to handle callback IRQs now.
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* Even if we were wrong, it would not enable the IRQ in
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* the GIC.
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*/
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pm_ipi_irq_enable(primary_proc);
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SMC_RET1(handle, (uint64_t)ret |
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((uint64_t)pm_ctx.api_version << 32));
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case PM_SET_CONFIGURATION:
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ret = pm_set_configuration(pm_arg[0]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_INIT_FINALIZE:
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ret = pm_init_finalize();
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SMC_RET1(handle, (uint64_t)ret);
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case PM_GET_NODE_STATUS:
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{
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uint32_t buff[3];
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ret = pm_get_node_status(pm_arg[0], buff);
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SMC_RET2(handle, (uint64_t)ret | ((uint64_t)buff[0] << 32),
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(uint64_t)buff[1] | ((uint64_t)buff[2] << 32));
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}
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case PM_GET_OP_CHARACTERISTIC:
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{
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uint32_t result;
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ret = pm_get_op_characteristic(pm_arg[0], pm_arg[1], &result);
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SMC_RET1(handle, (uint64_t)ret | ((uint64_t)result << 32));
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}
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case PM_REGISTER_NOTIFIER:
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ret = pm_register_notifier(pm_arg[0], pm_arg[1], pm_arg[2],
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pm_arg[3]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_RESET_ASSERT:
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ret = pm_reset_assert(pm_arg[0], pm_arg[1]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_RESET_GET_STATUS:
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{
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uint32_t reset_status;
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ret = pm_reset_get_status(pm_arg[0], &reset_status);
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SMC_RET1(handle, (uint64_t)ret |
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((uint64_t)reset_status << 32));
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}
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/* PM memory access functions */
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case PM_MMIO_WRITE:
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ret = pm_mmio_write(pm_arg[0], pm_arg[1], pm_arg[2]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_MMIO_READ:
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{
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uint32_t value;
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ret = pm_mmio_read(pm_arg[0], &value);
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SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
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}
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case PM_FPGA_LOAD:
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ret = pm_fpga_load(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_FPGA_GET_STATUS:
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{
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uint32_t value;
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ret = pm_fpga_get_status(&value);
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SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
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}
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case PM_GET_CHIPID:
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{
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uint32_t result[2];
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ret = pm_get_chipid(result);
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SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32),
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result[1]);
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}
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case PM_SECURE_RSA_AES:
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ret = pm_secure_rsaaes(pm_arg[0], pm_arg[1], pm_arg[2],
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pm_arg[3]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_PINCTRL_REQUEST:
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ret = pm_pinctrl_request(pm_arg[0]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_PINCTRL_RELEASE:
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ret = pm_pinctrl_release(pm_arg[0]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_PINCTRL_GET_FUNCTION:
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{
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uint32_t value = 0;
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ret = pm_pinctrl_get_function(pm_arg[0], &value);
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SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
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}
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case PM_PINCTRL_SET_FUNCTION:
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ret = pm_pinctrl_set_function(pm_arg[0], pm_arg[1]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_PINCTRL_CONFIG_PARAM_GET:
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{
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uint32_t value;
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ret = pm_pinctrl_get_config(pm_arg[0], pm_arg[1], &value);
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SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
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}
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case PM_PINCTRL_CONFIG_PARAM_SET:
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ret = pm_pinctrl_set_config(pm_arg[0], pm_arg[1], pm_arg[2]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_IOCTL:
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{
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uint32_t value;
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ret = pm_ioctl(pm_arg[0], pm_arg[1], pm_arg[2],
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pm_arg[3], &value);
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SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
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}
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case PM_QUERY_DATA:
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{
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uint32_t data[4] = { 0 };
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ret = pm_query_data(pm_arg[0], pm_arg[1], pm_arg[2],
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pm_arg[3], data);
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SMC_RET2(handle, (uint64_t)data[0] | ((uint64_t)data[1] << 32),
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(uint64_t)data[2] | ((uint64_t)data[3] << 32));
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}
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case PM_CLOCK_ENABLE:
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ret = pm_clock_enable(pm_arg[0]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_CLOCK_DISABLE:
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ret = pm_clock_disable(pm_arg[0]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_CLOCK_GETSTATE:
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{
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uint32_t value;
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ret = pm_clock_getstate(pm_arg[0], &value);
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SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
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}
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case PM_CLOCK_SETDIVIDER:
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ret = pm_clock_setdivider(pm_arg[0], pm_arg[1]);
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SMC_RET1(handle, (uint64_t)ret);
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case PM_CLOCK_GETDIVIDER:
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{
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uint32_t value;
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ret = pm_clock_getdivider(pm_arg[0], &value);
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SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
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}
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case PM_CLOCK_SETRATE:
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ret = pm_clock_setrate(pm_arg[0],
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((uint64_t)pm_arg[2]) << 32 | pm_arg[1]);
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SMC_RET1(handle, (uint64_t)ret);
|
|
|
|
case PM_CLOCK_GETRATE:
|
|
{
|
|
uint64_t value;
|
|
|
|
ret = pm_clock_getrate(pm_arg[0], &value);
|
|
SMC_RET2(handle, (uint64_t)ret |
|
|
(((uint64_t)value & 0xFFFFFFFFU) << 32U),
|
|
(value >> 32U) & 0xFFFFFFFFU);
|
|
|
|
}
|
|
|
|
case PM_CLOCK_SETPARENT:
|
|
ret = pm_clock_setparent(pm_arg[0], pm_arg[1]);
|
|
SMC_RET1(handle, (uint64_t)ret);
|
|
|
|
case PM_CLOCK_GETPARENT:
|
|
{
|
|
uint32_t value;
|
|
|
|
ret = pm_clock_getparent(pm_arg[0], &value);
|
|
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
|
|
}
|
|
|
|
case PM_GET_TRUSTZONE_VERSION:
|
|
SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS |
|
|
((uint64_t)ZYNQMP_TZ_VERSION << 32));
|
|
|
|
case PM_SET_SUSPEND_MODE:
|
|
ret = pm_set_suspend_mode(pm_arg[0]);
|
|
SMC_RET1(handle, (uint64_t)ret);
|
|
|
|
case PM_SECURE_SHA:
|
|
ret = pm_sha_hash(pm_arg[0], pm_arg[1], pm_arg[2],
|
|
pm_arg[3]);
|
|
SMC_RET1(handle, (uint64_t)ret);
|
|
|
|
case PM_SECURE_RSA:
|
|
ret = pm_rsa_core(pm_arg[0], pm_arg[1], pm_arg[2],
|
|
pm_arg[3]);
|
|
SMC_RET1(handle, (uint64_t)ret);
|
|
|
|
case PM_SECURE_IMAGE:
|
|
{
|
|
uint32_t result[2];
|
|
|
|
ret = pm_secure_image(pm_arg[0], pm_arg[1], pm_arg[2],
|
|
pm_arg[3], &result[0]);
|
|
SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32),
|
|
result[1]);
|
|
}
|
|
|
|
case PM_FPGA_READ:
|
|
{
|
|
uint32_t value;
|
|
|
|
ret = pm_fpga_read(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3],
|
|
&value);
|
|
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
|
|
}
|
|
|
|
case PM_SECURE_AES:
|
|
{
|
|
uint32_t value;
|
|
|
|
ret = pm_aes_engine(pm_arg[0], pm_arg[1], &value);
|
|
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
|
|
}
|
|
|
|
case PM_PLL_SET_PARAMETER:
|
|
ret = pm_pll_set_parameter(pm_arg[0], pm_arg[1], pm_arg[2]);
|
|
SMC_RET1(handle, (uint64_t)ret);
|
|
|
|
case PM_PLL_GET_PARAMETER:
|
|
{
|
|
uint32_t value;
|
|
|
|
ret = pm_pll_get_parameter(pm_arg[0], pm_arg[1], &value);
|
|
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value << 32));
|
|
}
|
|
|
|
case PM_PLL_SET_MODE:
|
|
ret = pm_pll_set_mode(pm_arg[0], pm_arg[1]);
|
|
SMC_RET1(handle, (uint64_t)ret);
|
|
|
|
case PM_PLL_GET_MODE:
|
|
{
|
|
uint32_t mode;
|
|
|
|
ret = pm_pll_get_mode(pm_arg[0], &mode);
|
|
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32));
|
|
}
|
|
|
|
default:
|
|
WARN("Unimplemented PM Service Call: 0x%x\n", smc_fid);
|
|
SMC_RET1(handle, SMC_UNK);
|
|
}
|
|
}
|