321 lines
6.7 KiB
C
321 lines
6.7 KiB
C
/*
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* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* ZynqMP power management enums and defines */
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#ifndef PM_DEFS_H
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#define PM_DEFS_H
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/*********************************************************************
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* Macro definitions
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********************************************************************/
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/*
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* Version number is a 32bit value, like:
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* (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR
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*/
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#define PM_VERSION_MAJOR 1
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#define PM_VERSION_MINOR 0
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#define PM_VERSION ((PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR)
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/* Capabilities for RAM */
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#define PM_CAP_ACCESS 0x1U
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#define PM_CAP_CONTEXT 0x2U
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#define MAX_LATENCY (~0U)
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#define MAX_QOS 100U
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/* State arguments of the self suspend */
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#define PM_STATE_CPU_IDLE 0x0U
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#define PM_STATE_SUSPEND_TO_RAM 0xFU
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/*********************************************************************
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* Enum definitions
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********************************************************************/
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enum pm_api_id {
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/* Miscellaneous API functions: */
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PM_GET_API_VERSION = 1, /* Do not change or move */
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PM_SET_CONFIGURATION,
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PM_GET_NODE_STATUS,
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PM_GET_OP_CHARACTERISTIC,
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PM_REGISTER_NOTIFIER,
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/* API for suspending of PUs: */
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PM_REQ_SUSPEND,
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PM_SELF_SUSPEND,
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PM_FORCE_POWERDOWN,
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PM_ABORT_SUSPEND,
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PM_REQ_WAKEUP,
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PM_SET_WAKEUP_SOURCE,
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PM_SYSTEM_SHUTDOWN,
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/* API for managing PM slaves: */
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PM_REQ_NODE,
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PM_RELEASE_NODE,
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PM_SET_REQUIREMENT,
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PM_SET_MAX_LATENCY,
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/* Direct control API functions: */
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PM_RESET_ASSERT,
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PM_RESET_GET_STATUS,
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PM_MMIO_WRITE,
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PM_MMIO_READ,
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PM_INIT_FINALIZE,
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PM_FPGA_LOAD,
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PM_FPGA_GET_STATUS,
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PM_GET_CHIPID,
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PM_SECURE_RSA_AES,
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PM_SECURE_SHA,
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PM_SECURE_RSA,
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PM_PINCTRL_REQUEST,
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PM_PINCTRL_RELEASE,
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PM_PINCTRL_GET_FUNCTION,
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PM_PINCTRL_SET_FUNCTION,
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PM_PINCTRL_CONFIG_PARAM_GET,
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PM_PINCTRL_CONFIG_PARAM_SET,
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PM_IOCTL,
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/* API to query information from firmware */
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PM_QUERY_DATA,
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/* Clock control API functions */
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PM_CLOCK_ENABLE,
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PM_CLOCK_DISABLE,
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PM_CLOCK_GETSTATE,
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PM_CLOCK_SETDIVIDER,
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PM_CLOCK_GETDIVIDER,
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PM_CLOCK_SETRATE,
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PM_CLOCK_GETRATE,
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PM_CLOCK_SETPARENT,
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PM_CLOCK_GETPARENT,
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PM_SECURE_IMAGE,
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/* FPGA PL Readback */
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PM_FPGA_READ,
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PM_SECURE_AES,
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/* PLL control API functions */
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PM_PLL_SET_PARAMETER,
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PM_PLL_GET_PARAMETER,
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PM_PLL_SET_MODE,
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PM_PLL_GET_MODE,
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PM_API_MAX
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};
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enum pm_node_id {
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NODE_UNKNOWN = 0,
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NODE_APU,
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NODE_APU_0,
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NODE_APU_1,
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NODE_APU_2,
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NODE_APU_3,
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NODE_RPU,
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NODE_RPU_0,
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NODE_RPU_1,
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NODE_PLD,
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NODE_FPD,
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NODE_OCM_BANK_0,
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NODE_OCM_BANK_1,
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NODE_OCM_BANK_2,
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NODE_OCM_BANK_3,
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NODE_TCM_0_A,
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NODE_TCM_0_B,
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NODE_TCM_1_A,
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NODE_TCM_1_B,
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NODE_L2,
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NODE_GPU_PP_0,
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NODE_GPU_PP_1,
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NODE_USB_0,
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NODE_USB_1,
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NODE_TTC_0,
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NODE_TTC_1,
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NODE_TTC_2,
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NODE_TTC_3,
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NODE_SATA,
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NODE_ETH_0,
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NODE_ETH_1,
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NODE_ETH_2,
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NODE_ETH_3,
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NODE_UART_0,
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NODE_UART_1,
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NODE_SPI_0,
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NODE_SPI_1,
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NODE_I2C_0,
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NODE_I2C_1,
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NODE_SD_0,
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NODE_SD_1,
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NODE_DP,
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NODE_GDMA,
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NODE_ADMA,
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NODE_NAND,
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NODE_QSPI,
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NODE_GPIO,
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NODE_CAN_0,
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NODE_CAN_1,
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NODE_EXTERN,
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NODE_APLL,
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NODE_VPLL,
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NODE_DPLL,
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NODE_RPLL,
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NODE_IOPLL,
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NODE_DDR,
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NODE_IPI_APU,
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NODE_IPI_RPU_0,
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NODE_GPU,
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NODE_PCIE,
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NODE_PCAP,
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NODE_RTC,
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NODE_LPD,
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NODE_VCU,
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NODE_IPI_RPU_1,
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NODE_IPI_PL_0,
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NODE_IPI_PL_1,
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NODE_IPI_PL_2,
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NODE_IPI_PL_3,
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NODE_PL,
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NODE_GEM_TSU,
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NODE_SWDT_0,
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NODE_SWDT_1,
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NODE_CSU,
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NODE_PJTAG,
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NODE_TRACE,
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NODE_TESTSCAN,
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NODE_PMU,
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NODE_MAX,
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};
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enum pm_request_ack {
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REQ_ACK_NO = 1,
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REQ_ACK_BLOCKING,
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REQ_ACK_NON_BLOCKING,
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};
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enum pm_abort_reason {
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ABORT_REASON_WKUP_EVENT = 100,
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ABORT_REASON_PU_BUSY,
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ABORT_REASON_NO_PWRDN,
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ABORT_REASON_UNKNOWN,
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};
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enum pm_suspend_reason {
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SUSPEND_REASON_PU_REQ = 201,
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SUSPEND_REASON_ALERT,
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SUSPEND_REASON_SYS_SHUTDOWN,
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};
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enum pm_ram_state {
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PM_RAM_STATE_OFF = 1,
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PM_RAM_STATE_RETENTION,
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PM_RAM_STATE_ON,
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};
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enum pm_opchar_type {
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PM_OPCHAR_TYPE_POWER = 1,
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PM_OPCHAR_TYPE_TEMP,
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PM_OPCHAR_TYPE_LATENCY,
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};
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/**
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* @PM_RET_SUCCESS: success
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* @PM_RET_ERROR_ARGS: illegal arguments provided
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* @PM_RET_ERROR_ACCESS: access rights violation
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* @PM_RET_ERROR_TIMEOUT: timeout in communication with PMU
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* @PM_RET_ERROR_NOTSUPPORTED: feature not supported
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* @PM_RET_ERROR_PROC: node is not a processor node
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* @PM_RET_ERROR_API_ID: illegal API ID
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* @PM_RET_ERROR_OTHER: other error
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*/
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enum pm_ret_status {
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PM_RET_SUCCESS,
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PM_RET_ERROR_ARGS,
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PM_RET_ERROR_ACCESS,
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PM_RET_ERROR_TIMEOUT,
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PM_RET_ERROR_NOTSUPPORTED,
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PM_RET_ERROR_PROC,
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PM_RET_ERROR_API_ID,
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PM_RET_ERROR_FAILURE,
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PM_RET_ERROR_COMMUNIC,
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PM_RET_ERROR_DOUBLEREQ,
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PM_RET_ERROR_OTHER,
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};
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/**
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* @PM_INITIAL_BOOT: boot is a fresh system startup
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* @PM_RESUME: boot is a resume
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* @PM_BOOT_ERROR: error, boot cause cannot be identified
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*/
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enum pm_boot_status {
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PM_INITIAL_BOOT,
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PM_RESUME,
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PM_BOOT_ERROR,
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};
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/**
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* @PMF_SHUTDOWN_TYPE_SHUTDOWN: shutdown
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* @PMF_SHUTDOWN_TYPE_RESET: reset/reboot
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* @PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY: set the shutdown/reboot scope
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*/
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enum pm_shutdown_type {
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PMF_SHUTDOWN_TYPE_SHUTDOWN,
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PMF_SHUTDOWN_TYPE_RESET,
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PMF_SHUTDOWN_TYPE_SETSCOPE_ONLY,
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};
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/**
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* @PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM: shutdown/reboot APU subsystem only
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* @PMF_SHUTDOWN_SUBTYPE_PS_ONLY: shutdown/reboot entire PS (but not PL)
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* @PMF_SHUTDOWN_SUBTYPE_SYSTEM: shutdown/reboot entire system
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*/
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enum pm_shutdown_subtype {
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PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM,
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PMF_SHUTDOWN_SUBTYPE_PS_ONLY,
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PMF_SHUTDOWN_SUBTYPE_SYSTEM,
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};
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/**
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* @PM_PLL_PARAM_DIV2: Enable for divide by 2 function inside the PLL
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* @PM_PLL_PARAM_FBDIV: Feedback divisor integer portion for the PLL
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* @PM_PLL_PARAM_DATA: Feedback divisor fractional portion for the PLL
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* @PM_PLL_PARAM_PRE_SRC: Clock source for PLL input
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* @PM_PLL_PARAM_POST_SRC: Clock source for PLL Bypass mode
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* @PM_PLL_PARAM_LOCK_DLY: Lock circuit config settings for lock windowsize
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* @PM_PLL_PARAM_LOCK_CNT: Lock circuit counter setting
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* @PM_PLL_PARAM_LFHF: PLL loop filter high frequency capacitor control
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* @PM_PLL_PARAM_CP: PLL charge pump control
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* @PM_PLL_PARAM_RES: PLL loop filter resistor control
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*/
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enum pm_pll_param {
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PM_PLL_PARAM_DIV2,
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PM_PLL_PARAM_FBDIV,
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PM_PLL_PARAM_DATA,
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PM_PLL_PARAM_PRE_SRC,
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PM_PLL_PARAM_POST_SRC,
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PM_PLL_PARAM_LOCK_DLY,
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PM_PLL_PARAM_LOCK_CNT,
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PM_PLL_PARAM_LFHF,
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PM_PLL_PARAM_CP,
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PM_PLL_PARAM_RES,
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PM_PLL_PARAM_MAX,
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};
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/**
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* @PM_PLL_MODE_RESET: PLL is in reset (not locked)
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* @PM_PLL_MODE_INTEGER: PLL is locked in integer mode
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* @PM_PLL_MODE_FRACTIONAL: PLL is locked in fractional mode
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*/
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enum pm_pll_mode {
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PM_PLL_MODE_RESET,
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PM_PLL_MODE_INTEGER,
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PM_PLL_MODE_FRACTIONAL,
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PM_PLL_MODE_MAX,
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};
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/**
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* @PM_CLOCK_DIV0_ID: Clock divider 0
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* @PM_CLOCK_DIV1_ID: Clock divider 1
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*/
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enum pm_clock_div_id {
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PM_CLOCK_DIV0_ID,
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PM_CLOCK_DIV1_ID,
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};
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#endif /* PM_DEFS_H */
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