169 lines
4.1 KiB
C
169 lines
4.1 KiB
C
/*
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* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <errno.h>
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#include <drivers/nand.h>
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#include <lib/utils.h>
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#include <plat/common/platform.h>
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#define SZ_512 0x200U
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#define SZ_64M 0x4000000U
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#if STM32MP_RAW_NAND || STM32MP_SPI_NAND
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static int get_data_from_otp(struct nand_device *nand_dev, bool is_slc)
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{
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uint32_t nand_param;
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/* Check if NAND parameters are stored in OTP */
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if (stm32_get_otp_value(NAND_OTP, &nand_param) != 0) {
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ERROR("BSEC: NAND_OTP Error\n");
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return -EACCES;
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}
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if (nand_param == 0U) {
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return 0;
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}
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if ((nand_param & NAND_PARAM_STORED_IN_OTP) == 0U) {
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goto ecc;
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}
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/* NAND parameter shall be read from OTP */
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if ((nand_param & NAND_WIDTH_MASK) != 0U) {
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nand_dev->buswidth = NAND_BUS_WIDTH_16;
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} else {
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nand_dev->buswidth = NAND_BUS_WIDTH_8;
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}
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switch ((nand_param & NAND_PAGE_SIZE_MASK) >> NAND_PAGE_SIZE_SHIFT) {
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case NAND_PAGE_SIZE_2K:
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nand_dev->page_size = 0x800U;
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break;
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case NAND_PAGE_SIZE_4K:
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nand_dev->page_size = 0x1000U;
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break;
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case NAND_PAGE_SIZE_8K:
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nand_dev->page_size = 0x2000U;
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break;
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default:
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ERROR("Cannot read NAND page size\n");
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return -EINVAL;
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}
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switch ((nand_param & NAND_BLOCK_SIZE_MASK) >> NAND_BLOCK_SIZE_SHIFT) {
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case NAND_BLOCK_SIZE_64_PAGES:
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nand_dev->block_size = 64U * nand_dev->page_size;
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break;
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case NAND_BLOCK_SIZE_128_PAGES:
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nand_dev->block_size = 128U * nand_dev->page_size;
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break;
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case NAND_BLOCK_SIZE_256_PAGES:
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nand_dev->block_size = 256U * nand_dev->page_size;
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break;
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default:
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ERROR("Cannot read NAND block size\n");
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return -EINVAL;
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}
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nand_dev->size = ((nand_param & NAND_BLOCK_NB_MASK) >>
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NAND_BLOCK_NB_SHIFT) *
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NAND_BLOCK_NB_UNIT * nand_dev->block_size;
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ecc:
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if (is_slc) {
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switch ((nand_param & NAND_ECC_BIT_NB_MASK) >>
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NAND_ECC_BIT_NB_SHIFT) {
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case NAND_ECC_BIT_NB_1_BITS:
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nand_dev->ecc.max_bit_corr = 1U;
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break;
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case NAND_ECC_BIT_NB_4_BITS:
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nand_dev->ecc.max_bit_corr = 4U;
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break;
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case NAND_ECC_BIT_NB_8_BITS:
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nand_dev->ecc.max_bit_corr = 8U;
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break;
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case NAND_ECC_ON_DIE:
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nand_dev->ecc.mode = NAND_ECC_ONDIE;
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break;
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default:
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if (nand_dev->ecc.max_bit_corr == 0U) {
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ERROR("No valid eccbit number\n");
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return -EINVAL;
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}
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}
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} else {
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/* Selected multiple plane NAND */
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if ((nand_param & NAND_PLANE_BIT_NB_MASK) != 0U) {
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nand_dev->nb_planes = 2U;
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} else {
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nand_dev->nb_planes = 1U;
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}
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}
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VERBOSE("OTP: Block %i Page %i Size %lli\n", nand_dev->block_size,
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nand_dev->page_size, nand_dev->size);
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return 0;
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}
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#endif /* STM32MP_RAW_NAND || STM32MP_SPI_NAND */
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#if STM32MP_RAW_NAND
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int plat_get_raw_nand_data(struct rawnand_device *device)
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{
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device->nand_dev->ecc.mode = NAND_ECC_HW;
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device->nand_dev->ecc.size = SZ_512;
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return get_data_from_otp(device->nand_dev, true);
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}
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#endif
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#if STM32MP_SPI_NAND
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int plat_get_spi_nand_data(struct spinand_device *device)
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{
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zeromem(&device->spi_read_cache_op, sizeof(struct spi_mem_op));
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device->spi_read_cache_op.cmd.opcode = SPI_NAND_OP_READ_FROM_CACHE_4X;
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device->spi_read_cache_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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device->spi_read_cache_op.addr.nbytes = 2U;
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device->spi_read_cache_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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device->spi_read_cache_op.dummy.nbytes = 1U;
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device->spi_read_cache_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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device->spi_read_cache_op.data.buswidth = SPI_MEM_BUSWIDTH_4_LINE;
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device->spi_read_cache_op.data.dir = SPI_MEM_DATA_IN;
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return get_data_from_otp(device->nand_dev, false);
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}
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#endif
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#if STM32MP_SPI_NOR
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int plat_get_nor_data(struct nor_device *device)
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{
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device->size = SZ_64M;
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zeromem(&device->read_op, sizeof(struct spi_mem_op));
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device->read_op.cmd.opcode = SPI_NOR_OP_READ_1_1_4;
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device->read_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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device->read_op.addr.nbytes = 3U;
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device->read_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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device->read_op.dummy.nbytes = 1U;
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device->read_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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device->read_op.data.buswidth = SPI_MEM_BUSWIDTH_4_LINE;
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device->read_op.data.dir = SPI_MEM_DATA_IN;
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return 0;
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}
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#endif
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