670 lines
17 KiB
C
670 lines
17 KiB
C
/*
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <string.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/desc_image_load.h>
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#include <drivers/delay_timer.h>
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#include <drivers/generic_delay_timer.h>
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#include <drivers/st/bsec.h>
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#include <drivers/st/stm32_console.h>
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#include <drivers/st/stm32_iwdg.h>
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#include <drivers/st/stm32mp_clkfunc.h>
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#include <drivers/st/stm32mp_pmic.h>
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#include <drivers/st/stm32mp_reset.h>
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#include <drivers/st/stm32mp1_clk.h>
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#include <drivers/st/stm32mp1_pwr.h>
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#include <drivers/st/stm32mp1_ram.h>
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#if STM32MP_UART_PROGRAMMER
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#include <drivers/st/stm32mp1xx_hal_uart.h>
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#endif
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#include <drivers/st/stpmic1.h>
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#include <lib/mmio.h>
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#include <lib/optee_utils.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include <boot_api.h>
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#include <stm32mp1_context.h>
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#include <stm32mp1_dbgmcu.h>
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#define PWRLP_TEMPO_5_HSI 5
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#define TIMEOUT_US_1MS U(1000)
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static const char debug_msg[626] = {
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"***************************************************\n"
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"** NOTICE NOTICE NOTICE NOTICE NOTICE **\n"
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"** **\n"
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"** DEBUG ACCESS PORT IS OPEN! **\n"
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"** This boot image is only for debugging purpose **\n"
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"** and is unsafe for production use. **\n"
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"** **\n"
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"** If you see this message and you are not **\n"
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"** debugging report this immediately to your **\n"
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"** vendor! **\n"
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"** **\n"
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"***************************************************\n"
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};
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static struct console_stm32 console;
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static enum boot_device_e boot_device = BOOT_DEVICE_BOARD;
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static bool wakeup_standby;
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static void print_reset_reason(void)
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{
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uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR);
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if (rstsr == 0U) {
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WARN("Reset reason unknown\n");
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return;
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}
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INFO("Reset reason (0x%x):\n", rstsr);
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if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) {
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if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) {
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INFO("System exits from STANDBY\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) {
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INFO("MPU exits from CSTANDBY\n");
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return;
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}
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}
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if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) {
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INFO(" Power-on Reset (rst_por)\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) {
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INFO(" Brownout Reset (rst_bor)\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) {
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if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
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INFO(" System reset generated by MCU (MCSYSRST)\n");
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} else {
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INFO(" Local reset generated by MCU (MCSYSRST)\n");
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}
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
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INFO(" System reset generated by MPU (MPSYSRST)\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) {
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INFO(" Reset due to a clock failure on HSE\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) {
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INFO(" IWDG1 Reset (rst_iwdg1)\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) {
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INFO(" IWDG2 Reset (rst_iwdg2)\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) {
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INFO(" MPU Processor 0 Reset\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) {
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INFO(" MPU Processor 1 Reset\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
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INFO(" Pad Reset from NRST\n");
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return;
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}
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if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) {
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INFO(" Reset due to a failure of VDD_CORE\n");
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return;
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}
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ERROR(" Unidentified reset reason\n");
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}
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enum boot_device_e get_boot_device(void)
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{
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return boot_device;
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}
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void bl2_el3_early_platform_setup(u_register_t arg0,
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u_register_t arg1 __unused,
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u_register_t arg2 __unused,
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u_register_t arg3 __unused)
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{
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stm32mp_save_boot_ctx_address(arg0);
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}
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void bl2_platform_setup(void)
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{
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int ret;
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/*
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* Map DDR non cacheable during its initialisation to avoid
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* speculative loads before accesses are fully setup.
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*/
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ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
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STM32MP_DDR_MAX_SIZE,
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MT_NON_CACHEABLE | MT_RW | MT_NS);
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assert(ret == 0);
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ret = stm32mp1_ddr_probe();
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if (ret < 0) {
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ERROR("Invalid DDR init: error %d\n", ret);
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panic();
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}
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ret = mmap_remove_dynamic_region(STM32MP_DDR_BASE,
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STM32MP_DDR_MAX_SIZE);
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assert(ret == 0);
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#ifdef AARCH32_SP_OPTEE
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INFO("BL2 runs OP-TEE setup\n");
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/* Map non secure DDR for BL33 load, now with cacheable attribute */
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ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
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dt_get_ddr_size() - STM32MP_DDR_S_SIZE -
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STM32MP_DDR_SHMEM_SIZE,
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MT_MEMORY | MT_RW | MT_NS);
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assert(ret == 0);
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ret = mmap_add_dynamic_region(STM32MP_DDR_BASE + dt_get_ddr_size() -
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STM32MP_DDR_S_SIZE -
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STM32MP_DDR_SHMEM_SIZE,
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STM32MP_DDR_BASE + dt_get_ddr_size() -
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STM32MP_DDR_S_SIZE -
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STM32MP_DDR_SHMEM_SIZE,
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STM32MP_DDR_S_SIZE,
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MT_MEMORY | MT_RW | MT_SECURE);
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assert(ret == 0);
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/* Initialize tzc400 after DDR initialization */
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stm32mp1_security_setup();
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#else
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INFO("BL2 runs SP_MIN setup\n");
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/* Map non secure DDR for BL33 load, now with cacheable attribute */
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ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
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dt_get_ddr_size(),
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MT_MEMORY | MT_RW | MT_NS);
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assert(ret == 0);
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#endif
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if ((dt_pmic_status() > 0) && (!wakeup_standby)) {
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configure_pmic();
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}
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}
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static void update_monotonic_counter(void)
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{
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uint32_t version;
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uint32_t otp;
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CASSERT(STM32_TF_VERSION <= MAX_MONOTONIC_VALUE,
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assert_stm32mp1_monotonic_counter_reach_max);
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/* Check if monotonic counter needs to be incremented */
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if (stm32_get_otp_index(MONOTONIC_OTP, &otp, NULL) != 0) {
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panic();
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}
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if (stm32_get_otp_value(MONOTONIC_OTP, &version) != 0) {
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panic();
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}
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if ((version + 1U) < BIT(STM32_TF_VERSION)) {
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uint32_t result;
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/* Need to increment the monotonic counter. */
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version = BIT(STM32_TF_VERSION) - 1U;
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result = bsec_program_otp(version, otp);
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if (result != BSEC_OK) {
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ERROR("BSEC: MONOTONIC_OTP program Error %i\n",
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result);
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panic();
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}
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INFO("Monotonic counter has been incremented (value 0x%x)\n",
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version);
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}
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}
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static void initialize_clock(void)
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{
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uint32_t voltage_mv = 0U;
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uint32_t freq_khz = 0U;
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int ret = 0;
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if (wakeup_standby) {
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ret = stm32_get_pll1_settings_from_context();
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}
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/*
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* If no pre-defined PLL1 settings in DT, find the highest frequency
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* in the OPP table (in DT, compatible with plaform capabilities, or
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* in structure restored in RAM), and set related CPU supply voltage.
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* If PLL1 settings found in DT, we consider CPU supply voltage in DT
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* is consistent with it.
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*/
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if ((ret == 0) && !fdt_is_pll1_predefined()) {
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if (wakeup_standby) {
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ret = stm32mp1_clk_get_maxfreq_opp(&freq_khz,
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&voltage_mv);
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} else {
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ret = dt_get_max_opp_freqvolt(&freq_khz, &voltage_mv);
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}
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if (ret != 0) {
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panic();
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}
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if (dt_pmic_status() > 0) {
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int read_voltage;
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const char *name;
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name = stm32mp_get_cpu_supply_name();
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if (name == NULL) {
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panic();
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}
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read_voltage = stpmic1_regulator_voltage_get(name);
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if (read_voltage < 0) {
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panic();
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}
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if (voltage_mv != (uint32_t)read_voltage) {
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if (stpmic1_regulator_voltage_set(name,
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(uint16_t)voltage_mv) != 0) {
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panic();
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}
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}
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}
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}
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if (stm32mp1_clk_init(freq_khz) < 0) {
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panic();
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}
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}
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static void reset_uart(uint32_t reset)
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{
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if (stm32mp_reset_assert_to(reset, TIMEOUT_US_1MS)) {
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panic();
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}
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udelay(2);
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if (stm32mp_reset_deassert_to(reset, TIMEOUT_US_1MS)) {
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panic();
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}
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mdelay(1);
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}
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void bl2_el3_plat_arch_setup(void)
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{
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int32_t result;
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struct dt_node_info dt_uart_info;
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const char *board_model;
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boot_api_context_t *boot_context =
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(boot_api_context_t *)stm32mp_get_boot_ctx_address();
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uint32_t clk_rate;
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uintptr_t pwr_base;
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uintptr_t rcc_base;
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uint32_t bkpr_core1_magic =
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tamp_bkpr(BOOT_API_CORE1_MAGIC_NUMBER_TAMP_BCK_REG_IDX);
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uint32_t bkpr_core1_addr =
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tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX);
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mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
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BL_CODE_END - BL_CODE_BASE,
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MT_CODE | MT_SECURE);
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#ifdef AARCH32_SP_OPTEE
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mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE,
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STM32MP_OPTEE_SIZE,
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MT_MEMORY | MT_RW | MT_SECURE);
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#else
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/* Prevent corruption of preloaded BL32 */
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mmap_add_region(BL32_BASE, BL32_BASE,
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BL32_LIMIT - BL32_BASE,
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MT_RO_DATA | MT_SECURE);
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#endif
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/* Prevent corruption of preloaded Device Tree */
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mmap_add_region(DTB_BASE, DTB_BASE,
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DTB_LIMIT - DTB_BASE,
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MT_RO_DATA | MT_SECURE);
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configure_mmu();
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if (dt_open_and_check() < 0) {
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panic();
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}
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pwr_base = stm32mp_pwr_base();
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rcc_base = stm32mp_rcc_base();
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/* Clear Stop Request bits to correctly manage low-power exit */
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mmio_write_32(rcc_base + RCC_MP_SREQCLRR,
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(uint32_t)(RCC_MP_SREQCLRR_STPREQ_P0 |
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RCC_MP_SREQCLRR_STPREQ_P1));
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/*
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* Disable the backup domain write protection.
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* The protection is enable at each reset by hardware
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* and must be disabled by software.
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*/
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mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP);
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while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) {
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;
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}
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/*
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* Configure Standby mode available for MCU by default
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* and allow to switch in standby SoC in all case
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*/
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mmio_setbits_32(pwr_base + PWR_MCUCR, PWR_MCUCR_PDDS);
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if (bsec_probe() != 0) {
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panic();
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}
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/* Reset backup domain on cold boot cases */
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if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) {
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mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
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while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) ==
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0U) {
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;
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}
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mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
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}
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/* Wait 5 HSI periods before re-enabling PLLs after STOP modes */
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mmio_clrsetbits_32(rcc_base + RCC_PWRLPDLYCR,
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RCC_PWRLPDLYCR_PWRLP_DLY_MASK,
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PWRLP_TEMPO_5_HSI);
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/* Disable retention and backup RAM content after standby */
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mmio_clrbits_32(pwr_base + PWR_CR2, PWR_CR2_BREN | PWR_CR2_RREN);
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/* Disable MCKPROT */
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mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT);
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/* Enable BKP Register protection */
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mmio_write_32(TAMP_SMCR,
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TAMP_BKP_SEC_NUMBER << TAMP_BKP_SEC_WDPROT_SHIFT |
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TAMP_BKP_SEC_NUMBER << TAMP_BKP_SEC_RWDPROT_SHIFT);
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if ((boot_context->boot_action !=
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BOOT_API_CTX_BOOT_ACTION_WAKEUP_CSTANDBY) &&
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(boot_context->boot_action !=
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BOOT_API_CTX_BOOT_ACTION_WAKEUP_STANDBY)) {
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mmio_write_32(bkpr_core1_addr, 0);
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mmio_write_32(bkpr_core1_magic, 0);
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}
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wakeup_standby = (mmio_read_32(bkpr_core1_addr) != 0U);
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generic_delay_timer_init();
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#if STM32MP_USB_PROGRAMMER
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if (boot_context->boot_interface_selected ==
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BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) {
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boot_device = BOOT_DEVICE_USB;
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}
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#endif
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#if STM32MP_UART_PROGRAMMER
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/* Disable programmer UART before changing clock tree */
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if (boot_context->boot_interface_selected ==
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BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) {
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uintptr_t uart_prog_addr =
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get_uart_address(boot_context->boot_interface_instance);
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((USART_TypeDef *)uart_prog_addr)->CR1 &= ~USART_CR1_UE;
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}
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#endif
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if (stm32mp1_clk_probe() < 0) {
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panic();
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}
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if (dt_pmic_status() > 0) {
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initialize_pmic();
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}
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initialize_clock();
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result = dt_get_stdout_uart_info(&dt_uart_info);
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if ((result <= 0) ||
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(dt_uart_info.status == 0U) ||
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#if STM32MP_UART_PROGRAMMER
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((boot_context->boot_interface_selected ==
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BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) &&
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(get_uart_address(boot_context->boot_interface_instance) ==
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dt_uart_info.base)) ||
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#endif
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(dt_uart_info.clock < 0) ||
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(dt_uart_info.reset < 0)) {
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goto skip_console_init;
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}
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if (dt_set_stdout_pinctrl() != 0) {
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goto skip_console_init;
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}
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if (dt_uart_info.status == DT_DISABLED) {
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panic();
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} else if (dt_uart_info.status == DT_SECURE) {
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stm32mp_register_secure_periph_iomem(dt_uart_info.base);
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} else {
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stm32mp_register_non_secure_periph_iomem(dt_uart_info.base);
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}
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stm32mp_clk_enable((unsigned long)dt_uart_info.clock);
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reset_uart((uint32_t)dt_uart_info.reset);
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clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock);
|
|
|
|
if (console_stm32_register(dt_uart_info.base, clk_rate,
|
|
STM32MP_UART_BAUDRATE, &console) == 0) {
|
|
panic();
|
|
}
|
|
|
|
console_set_scope(&console.console, CONSOLE_FLAG_BOOT |
|
|
CONSOLE_FLAG_CRASH | CONSOLE_FLAG_TRANSLATE_CRLF);
|
|
|
|
stm32mp_print_cpuinfo();
|
|
|
|
board_model = dt_get_board_model();
|
|
if (board_model != NULL) {
|
|
NOTICE("Model: %s\n", board_model);
|
|
}
|
|
|
|
stm32mp_print_boardinfo();
|
|
|
|
#if TRUSTED_BOARD_BOOT
|
|
if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) {
|
|
NOTICE("Bootrom authentication %s\n",
|
|
(boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ?
|
|
"failed" : "succeeded");
|
|
}
|
|
#endif
|
|
|
|
skip_console_init:
|
|
#if !TRUSTED_BOARD_BOOT
|
|
if (stm32mp_is_closed_device()) {
|
|
/* Closed chip required authentication */
|
|
ERROR("Secured chip must enabled TRUSTED_BOARD_BOOT\n");
|
|
panic();
|
|
}
|
|
#endif
|
|
|
|
stm32mp1_syscfg_init();
|
|
|
|
if (stm32_iwdg_init() < 0) {
|
|
panic();
|
|
}
|
|
|
|
stm32_iwdg_refresh();
|
|
|
|
if (bsec_read_debug_conf() != 0U) {
|
|
result = stm32mp1_dbgmcu_freeze_iwdg2();
|
|
if (result != 0) {
|
|
INFO("IWDG2 freeze error : %i\n", result);
|
|
}
|
|
|
|
if (stm32mp_is_closed_device()) {
|
|
NOTICE("\n%s", debug_msg);
|
|
}
|
|
}
|
|
|
|
if (stm32_save_boot_interface(boot_context->boot_interface_selected,
|
|
boot_context->boot_interface_instance) !=
|
|
0) {
|
|
ERROR("Cannot save boot interface\n");
|
|
}
|
|
|
|
stm32mp1_arch_security_setup();
|
|
|
|
print_reset_reason();
|
|
|
|
update_monotonic_counter();
|
|
|
|
if (dt_pmic_status() > 0) {
|
|
initialize_pmic();
|
|
print_pmic_info_and_debug();
|
|
}
|
|
|
|
stm32mp_io_setup();
|
|
}
|
|
|
|
#if defined(AARCH32_SP_OPTEE)
|
|
static void set_mem_params_info(entry_point_info_t *ep_info,
|
|
image_info_t *unpaged, image_info_t *paged)
|
|
{
|
|
uintptr_t bl32_ep = 0;
|
|
|
|
/* Use the default dram setup if no valid ep found */
|
|
if (get_optee_header_ep(ep_info, &bl32_ep) &&
|
|
(bl32_ep >= STM32MP_OPTEE_BASE) &&
|
|
(bl32_ep < (STM32MP_OPTEE_BASE + STM32MP_OPTEE_SIZE))) {
|
|
assert((STM32MP_OPTEE_BASE >= BL2_LIMIT) ||
|
|
((STM32MP_OPTEE_BASE + STM32MP_OPTEE_SIZE) <= BL2_BASE));
|
|
|
|
unpaged->image_base = STM32MP_OPTEE_BASE;
|
|
unpaged->image_max_size = STM32MP_OPTEE_SIZE;
|
|
} else {
|
|
unpaged->image_base = STM32MP_DDR_BASE + dt_get_ddr_size() -
|
|
STM32MP_DDR_S_SIZE -
|
|
STM32MP_DDR_SHMEM_SIZE;
|
|
unpaged->image_max_size = STM32MP_DDR_S_SIZE;
|
|
}
|
|
paged->image_base = STM32MP_DDR_BASE + dt_get_ddr_size() -
|
|
STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE;
|
|
paged->image_max_size = STM32MP_DDR_S_SIZE;
|
|
}
|
|
#endif
|
|
|
|
/*******************************************************************************
|
|
* This function can be used by the platforms to update/use image
|
|
* information for given `image_id`.
|
|
******************************************************************************/
|
|
int bl2_plat_handle_post_image_load(unsigned int image_id)
|
|
{
|
|
int err = 0;
|
|
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
|
|
#if defined(AARCH32_SP_OPTEE)
|
|
bl_mem_params_node_t *bl32_mem_params;
|
|
bl_mem_params_node_t *pager_mem_params;
|
|
bl_mem_params_node_t *paged_mem_params;
|
|
#endif
|
|
|
|
assert(bl_mem_params != NULL);
|
|
|
|
#if TRUSTED_BOARD_BOOT
|
|
/* Clean header to avoid loaded header reused */
|
|
stm32mp_delete_loaded_header();
|
|
#endif
|
|
|
|
switch (image_id) {
|
|
case BL32_IMAGE_ID:
|
|
#if defined(AARCH32_SP_OPTEE)
|
|
bl_mem_params->ep_info.pc =
|
|
bl_mem_params->image_info.image_base;
|
|
|
|
pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
|
|
assert(pager_mem_params != NULL);
|
|
|
|
paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
|
|
assert(paged_mem_params != NULL);
|
|
|
|
set_mem_params_info(&bl_mem_params->ep_info,
|
|
&pager_mem_params->image_info,
|
|
&paged_mem_params->image_info);
|
|
|
|
err = parse_optee_header(&bl_mem_params->ep_info,
|
|
&pager_mem_params->image_info,
|
|
&paged_mem_params->image_info);
|
|
if (err) {
|
|
ERROR("OPTEE header parse error.\n");
|
|
panic();
|
|
}
|
|
|
|
/* Set optee boot info from parsed header data */
|
|
bl_mem_params->ep_info.pc =
|
|
pager_mem_params->image_info.image_base;
|
|
bl_mem_params->ep_info.args.arg0 =
|
|
paged_mem_params->image_info.image_base;
|
|
bl_mem_params->ep_info.args.arg1 = 0; /* Unused */
|
|
bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */
|
|
#endif
|
|
break;
|
|
|
|
case BL33_IMAGE_ID:
|
|
#ifdef AARCH32_SP_OPTEE
|
|
bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
|
|
assert(bl32_mem_params != NULL);
|
|
bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
|
|
#endif
|
|
|
|
flush_dcache_range(bl_mem_params->image_info.image_base,
|
|
bl_mem_params->image_info.image_max_size);
|
|
break;
|
|
|
|
default:
|
|
/* Do nothing in default case */
|
|
break;
|
|
}
|
|
|
|
return err;
|
|
}
|