285 lines
6.3 KiB
Plaintext
285 lines
6.3 KiB
Plaintext
#! armclang -E -x c
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#define PAGE_SIZE (1024 * 4)
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LR_START BL31_BASE
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{
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__BL31_START__ +0 FIXED EMPTY 0
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{
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/* placeholder */
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}
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/* BL31_BASE address must be aligned on a page boundary. */
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ScatterAssert((ImageBase(__BL31_START__) AND 0xFFF) == 0)
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}
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LR_TEXT BL31_BASE
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{
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__TEXT__ +0 FIXED
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{
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*(:gdef:bl31_entrypoint, +FIRST)
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*(.text*)
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*(.vectors)
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.ANY1(+RO-CODE)
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}
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__TEXT_EPILOGUE__ AlignExpr(+0, PAGE_SIZE) FIXED EMPTY 0
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{
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/* section delimiter */
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}
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}
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LR_RO_DATA +0
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{
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__RODATA__ AlignExpr(ImageLimit(LR_TEXT), 0) FIXED
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{
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*(.rodata*)
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.ANY2(+RO-DATA)
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}
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/* Ensure 8-byte alignment for descriptors and ensure inclusion */
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__RT_SVC_DESCS__ AlignExpr(ImageLimit(__RODATA__), 8) FIXED
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{
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*(rt_svc_descs)
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}
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#if ENABLE_PMF
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/* Ensure 8-byte alignment for descriptors and ensure inclusion */
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__PMF_SVC_DESCS__ AlignExpr(ImageLimit(__RT_SVC_DESCS__), 8) FIXED
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{
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*(pmf_svc_descs)
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}
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#endif /* ENABLE_PMF */
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/*
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* Ensure 8-byte alignment for cpu_ops so that its fields are also
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* aligned.
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*/
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__CPU_OPS__ AlignExpr(+0, 8) FIXED
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{
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*(cpu_ops)
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}
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/*
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* Keep the .got section in the RO section as it is patched
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* prior to enabling the MMU and having the .got in RO is better for
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* security. GOT is a table of addresses so ensure 8-byte alignment.
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*/
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__GOT__ AlignExpr(ImageLimit(__CPU_OPS__), 8) FIXED
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{
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*(.got)
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}
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/* Place pubsub sections for events */
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__PUBSUB_EVENTS__ AlignExpr(+0, 8) EMPTY 0
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{
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/* placeholder */
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}
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#include <lib/el3_runtime/pubsub_events.h>
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__RODATA_EPILOGUE__ AlignExpr(+0, PAGE_SIZE) FIXED EMPTY 0
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{
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/* section delimiter */
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}
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}
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/* cpu_ops must always be defined */
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ScatterAssert(ImageLength(__CPU_OPS__) > 0)
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#if ENABLE_SPM
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LR_SPM +0
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{
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/*
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* Exception vectors of the SPM shim layer. They must be aligned to a 2K
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* address, but we need to place them in a separate page so that we can set
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* individual permissions to them, so the actual alignment needed is 4K.
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*
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* There's no need to include this into the RO section of BL31 because it
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* doesn't need to be accessed by BL31.
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*/
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__SPM_SHIM_EXCEPTIONS__ AlignExpr(ImageLimit(LR_RO_DATA), PAGE_SIZE) FIXED
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{
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*(.spm_shim_exceptions)
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}
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__SPM_SHIM_EXCEPTIONS_EPILOGUE__ AlignExpr(ImageLimit(__SPM_SHIM_EXCEPTIONS__), PAGE_SIZE) FIXED
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{
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/* placeholder */
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}
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}
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#endif
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LR_RW_DATA +0
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{
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__DATA__ AlignExpr(+0, 16) FIXED
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{
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*(.data*)
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*(.constdata)
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*(locale$$data)
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}
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}
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LR_RELA +0
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{
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/*
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* .rela.dyn needs to come after .data for the read-elf utility to parse
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* this section correctly. Ensure 8-byte alignment so that the fields of
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* RELA data structure are aligned.
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*/
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__RELA__ AlignExpr(ImageLimit(LR_RW_DATA), 8) FIXED
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{
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*(.rela.dyn)
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}
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}
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#ifdef BL31_PROGBITS_LIMIT
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/* BL31 progbits has exceeded its limit. */
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ScatterAssert(ImageLimit(LR_RELA) <= BL31_PROGBITS_LIMIT)
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#endif
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LR_STACKS +0
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{
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__STACKS__ AlignExpr(+0, 64) FIXED
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{
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*(tzfw_normal_stacks)
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}
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}
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#define __BAKERY_LOCK_SIZE__ (ImageLimit(__BAKERY_LOCKS_EPILOGUE__) - \
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ImageBase(__BAKERY_LOCKS__))
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#define BAKERY_LOCK_SIZE (__BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1))
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#define __PMF_TIMESTAMP_SIZE__ (ImageLimit(__PMF_TIMESTAMP__) - \
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ImageBase(__PMF_TIMESTAMP__))
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#define PER_CPU_TIMESTAMP_SIZE (__PMF_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1))
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LR_BSS +0
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{
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__BSS__ AlignExpr(ImageLimit(LR_STACKS), 256) FIXED
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{
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*(.bss*)
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*(COMDAT)
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}
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#if !USE_COHERENT_MEM
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/*
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* Bakery locks are stored in normal .bss memory
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*
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* Each lock's data is spread across multiple cache lines, one per CPU,
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* but multiple locks can share the same cache line.
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* The compiler will allocate enough memory for one CPU's bakery locks,
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* the remaining cache lines are allocated by the linker script
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*/
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__BAKERY_LOCKS__ AlignExpr(ImageLimit(__BSS__), CACHE_WRITEBACK_GRANULE) FIXED
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{
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*(bakery_lock)
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}
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__BAKERY_LOCKS_EPILOGUE__ AlignExpr(ImageLimit(__BAKERY_LOCKS__), CACHE_WRITEBACK_GRANULE) FIXED EMPTY 0
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{
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/* section delimiter */
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}
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__PER_CPU_BAKERY_LOCKS__ ImageLimit(__BAKERY_LOCKS_EPILOGUE__) FIXED FILL 0 BAKERY_LOCK_SIZE
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{
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/* padded memory section to store per cpu bakery locks */
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}
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#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
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/* PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements */
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ScatterAssert(__PER_CPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE)
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#endif
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#endif
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#if ENABLE_PMF
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/*
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* Time-stamps are stored in normal .bss memory
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*
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* The compiler will allocate enough memory for one CPU's time-stamps,
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* the remaining memory for other CPU's is allocated by the
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* linker script
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*/
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__PMF_TIMESTAMP__ AlignExpr(+0, CACHE_WRITEBACK_GRANULE) FIXED EMPTY CACHE_WRITEBACK_GRANULE
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{
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/* store timestamps in this carved out memory */
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}
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__PMF_TIMESTAMP_EPILOGUE__ AlignExpr(ImageLimit(__PMF_TIMESTAMP__), CACHE_WRITEBACK_GRANULE) FIXED EMPTY 0
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{
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/*
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* placeholder to make __PMF_TIMESTAMP_START__ end on a
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* CACHE_WRITEBACK_GRANULE boundary
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*/
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}
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__PER_CPU_TIMESTAMPS__ +0 FIXED FILL 0 PER_CPU_TIMESTAMP_SIZE
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{
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/* padded memory section to store per cpu timestamps */
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}
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#endif /* ENABLE_PMF */
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}
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LR_XLAT_TABLE +0
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{
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xlat_table +0 FIXED
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{
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*(xlat_table)
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}
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}
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#if USE_COHERENT_MEM
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LR_COHERENT_RAM +0
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{
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/*
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* The base address of the coherent memory section must be page-aligned (4K)
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* to guarantee that the coherent data are stored on their own pages and
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* are not mixed with normal data. This is required to set up the correct
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* memory attributes for the coherent data page tables.
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*/
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__COHERENT_RAM__ AlignExpr(+0, PAGE_SIZE) FIXED
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{
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/*
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* Bakery locks are stored in coherent memory
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*
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* Each lock's data is contiguous and fully allocated by the compiler
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*/
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*(bakery_lock)
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*(tzfw_coherent_mem)
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}
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__COHERENT_RAM_EPILOGUE_UNALIGNED__ +0 FIXED EMPTY 0
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{
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/* section delimiter */
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}
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/*
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* Memory page(s) mapped to this section will be marked
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* as device memory. No other unexpected data must creep in.
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* Ensure the rest of the current memory page is unused.
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*/
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__COHERENT_RAM_EPILOGUE__ AlignExpr(ImageLimit(__COHERENT_RAM_START__), PAGE_SIZE) FIXED EMPTY 0
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{
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/* section delimiter */
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}
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}
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#endif
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LR_END +0
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{
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__BL31_END__ +0 FIXED EMPTY 0
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{
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/* placeholder */
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}
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/* BL31 image has exceeded its limit. */
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ScatterAssert(ImageLimit(__BL31_END__) <= BL31_LIMIT)
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}
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