493 lines
14 KiB
C
493 lines
14 KiB
C
/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <stddef.h>
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#include <string.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <bl31/bl31.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <cortex_a53.h>
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#include <cortex_a57.h>
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#include <denver.h>
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#include <drivers/console.h>
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#include <lib/mmio.h>
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#include <lib/utils.h>
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#include <lib/utils_def.h>
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#include <plat/common/platform.h>
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#include <memctrl.h>
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#include <profiler.h>
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#include <tegra_def.h>
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#include <tegra_platform.h>
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#include <tegra_private.h>
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/* length of Trusty's input parameters (in bytes) */
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#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
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extern void memcpy16(void *dest, const void *src, unsigned int length);
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/*******************************************************************************
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* Declarations of linker defined symbols which will help us find the layout
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* of trusted SRAM
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******************************************************************************/
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IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START);
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IMPORT_SYM(uint64_t, __RW_END__, BL31_RW_END);
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IMPORT_SYM(uint64_t, __RODATA_START__, BL31_RODATA_BASE);
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IMPORT_SYM(uint64_t, __RODATA_END__, BL31_RODATA_END);
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IMPORT_SYM(uint64_t, __TEXT_START__, TEXT_START);
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IMPORT_SYM(uint64_t, __TEXT_END__, TEXT_END);
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extern uint64_t tegra_bl31_phys_base;
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static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
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static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
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.tzdram_size = TZDRAM_SIZE
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};
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static unsigned long bl32_mem_size;
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static unsigned long bl32_boot_params;
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/*******************************************************************************
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* This variable holds the non-secure image entry address
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******************************************************************************/
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extern uint64_t ns_image_entrypoint;
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/*******************************************************************************
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* The following platform setup functions are weakly defined. They
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* provide typical implementations that will be overridden by a SoC.
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******************************************************************************/
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#pragma weak plat_early_platform_setup
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#pragma weak plat_get_bl31_params
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#pragma weak plat_get_bl31_plat_params
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#pragma weak plat_late_platform_setup
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void plat_early_platform_setup(void)
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{
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; /* do nothing */
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}
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struct tegra_bl31_params *plat_get_bl31_params(void)
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{
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return NULL;
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}
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plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
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{
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return NULL;
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}
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void plat_late_platform_setup(void)
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{
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; /* do nothing */
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}
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/*******************************************************************************
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* Return a pointer to the 'entry_point_info' structure of the next image for
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* security state specified. BL33 corresponds to the non-secure image type
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* while BL32 corresponds to the secure image type.
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******************************************************************************/
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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entry_point_info_t *ep = NULL;
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/* return BL32 entry point info if it is valid */
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if (type == NON_SECURE) {
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ep = &bl33_image_ep_info;
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} else if ((type == SECURE) && (bl32_image_ep_info.pc != 0U)) {
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ep = &bl32_image_ep_info;
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}
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return ep;
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}
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/*******************************************************************************
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* Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image
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* passes this platform specific information.
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******************************************************************************/
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plat_params_from_bl2_t *bl31_get_plat_params(void)
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{
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return &plat_bl31_params_from_bl2;
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}
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/*******************************************************************************
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* Perform any BL31 specific platform actions. Populate the BL33 and BL32 image
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* info.
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******************************************************************************/
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0;
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plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
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image_info_t bl32_img_info = { {0} };
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uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end, console_base;
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uint32_t console_clock;
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int32_t ret;
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static console_16550_t console;
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/*
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* For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
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* there's no argument to relay from a previous bootloader. Platforms
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* might use custom ways to get arguments, so provide handlers which
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* they can override.
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*/
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if (arg_from_bl2 == NULL) {
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arg_from_bl2 = plat_get_bl31_params();
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}
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if (plat_params == NULL) {
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plat_params = plat_get_bl31_plat_params();
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}
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/*
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* Copy BL3-3, BL3-2 entry point information.
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* They are stored in Secure RAM, in BL2's address space.
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*/
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assert(arg_from_bl2 != NULL);
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assert(arg_from_bl2->bl33_ep_info != NULL);
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bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
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if (arg_from_bl2->bl32_ep_info != NULL) {
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bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
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bl32_mem_size = arg_from_bl2->bl32_ep_info->args.arg0;
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bl32_boot_params = arg_from_bl2->bl32_ep_info->args.arg2;
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}
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/*
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* Parse platform specific parameters
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*/
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assert(plat_params != NULL);
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plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
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plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
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plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
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plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis;
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plat_bl31_params_from_bl2.sc7entry_fw_size = plat_params->sc7entry_fw_size;
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plat_bl31_params_from_bl2.sc7entry_fw_base = plat_params->sc7entry_fw_base;
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/*
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* It is very important that we run either from TZDRAM or TZSRAM base.
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* Add an explicit check here.
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*/
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if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) &&
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(TEGRA_TZRAM_BASE != BL31_BASE)) {
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panic();
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}
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/*
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* Reference clock used by the FPGAs is a lot slower.
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*/
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if (tegra_platform_is_fpga()) {
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console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
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} else {
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console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
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}
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/*
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* Get the base address of the UART controller to be used for the
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* console
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*/
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console_base = plat_get_console_from_id(plat_params->uart_id);
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if (console_base != 0U) {
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/*
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* Configure the UART port to be used as the console
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*/
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(void)console_16550_register(console_base,
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console_clock,
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TEGRA_CONSOLE_BAUDRATE,
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&console);
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console_set_scope(&console.console, CONSOLE_FLAG_BOOT |
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CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
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}
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/*
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* The previous bootloader passes the base address of the shared memory
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* location to store the boot profiler logs. Sanity check the
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* address and initialise the profiler library, if it looks ok.
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*/
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if (plat_params->boot_profiler_shmem_base != 0ULL) {
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ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base,
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PROFILER_SIZE_BYTES);
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if (ret == (int32_t)0) {
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/* store the membase for the profiler lib */
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plat_bl31_params_from_bl2.boot_profiler_shmem_base =
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plat_params->boot_profiler_shmem_base;
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/* initialise the profiler library */
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boot_profiler_init(plat_params->boot_profiler_shmem_base,
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TEGRA_TMRUS_BASE);
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}
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}
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/*
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* Add timestamp for platform early setup entry.
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*/
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boot_profiler_add_record("[TF] early setup entry");
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/*
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* Initialize delay timer
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*/
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tegra_delay_timer_init();
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/* Early platform setup for Tegra SoCs */
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plat_early_platform_setup();
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/*
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* Do initial security configuration to allow DRAM/device access.
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*/
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tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
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(uint32_t)plat_bl31_params_from_bl2.tzdram_size);
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/*
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* The previous bootloader might not have placed the BL32 image
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* inside the TZDRAM. We check the BL32 image info to find out
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* the base/PC values and relocate the image if necessary.
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*/
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if (arg_from_bl2->bl32_image_info != NULL) {
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bl32_img_info = *arg_from_bl2->bl32_image_info;
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/* Relocate BL32 if it resides outside of the TZDRAM */
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tzdram_start = plat_bl31_params_from_bl2.tzdram_base;
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tzdram_end = plat_bl31_params_from_bl2.tzdram_base +
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plat_bl31_params_from_bl2.tzdram_size;
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bl32_start = bl32_img_info.image_base;
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bl32_end = bl32_img_info.image_base + bl32_img_info.image_size;
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assert(tzdram_end > tzdram_start);
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assert(bl32_end > bl32_start);
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assert(bl32_image_ep_info.pc > tzdram_start);
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assert(bl32_image_ep_info.pc < tzdram_end);
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/* relocate BL32 */
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if ((bl32_start >= tzdram_end) || (bl32_end <= tzdram_start)) {
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INFO("Relocate BL32 to TZDRAM\n");
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(void)memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc,
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(void *)(uintptr_t)bl32_start,
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bl32_img_info.image_size);
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/* clean up non-secure intermediate buffer */
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zeromem((void *)(uintptr_t)bl32_start,
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bl32_img_info.image_size);
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}
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}
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/*
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* Add timestamp for platform early setup exit.
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*/
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boot_profiler_add_record("[TF] early setup exit");
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INFO("BL3-1: Boot CPU: %s Processor [%lx]\n",
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(((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK)
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== DENVER_IMPL) ? "Denver" : "ARM", read_mpidr());
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}
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#ifdef SPD_trusty
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void plat_trusty_set_boot_args(aapcs64_params_t *args)
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{
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args->arg0 = bl32_mem_size;
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args->arg1 = bl32_boot_params;
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args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
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/* update EKS size */
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if (args->arg4 != 0U) {
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args->arg2 = args->arg4;
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}
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/* Profiler Carveout Base */
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args->arg3 = args->arg5;
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}
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#endif
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/*******************************************************************************
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* Initialize the gic, configure the SCR.
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******************************************************************************/
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void bl31_platform_setup(void)
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{
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/*
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* Add timestamp for platform setup entry.
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*/
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boot_profiler_add_record("[TF] plat setup entry");
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/* Initialize the gic cpu and distributor interfaces */
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plat_gic_setup();
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/*
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* Setup secondary CPU POR infrastructure.
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*/
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plat_secondary_setup();
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/*
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* Initial Memory Controller configuration.
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*/
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tegra_memctrl_setup();
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/*
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* Set up the TZRAM memory aperture to allow only secure world
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* access
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*/
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tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE);
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/*
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* Late setup handler to allow platforms to performs additional
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* functionality.
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* This handler gets called with MMU enabled.
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*/
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plat_late_platform_setup();
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/*
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* Add timestamp for platform setup exit.
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*/
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boot_profiler_add_record("[TF] plat setup exit");
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INFO("BL3-1: Tegra platform setup complete\n");
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}
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/*******************************************************************************
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* Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit
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******************************************************************************/
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void bl31_plat_runtime_setup(void)
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{
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/*
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* During cold boot, it is observed that the arbitration
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* bit is set in the Memory controller leading to false
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* error interrupts in the non-secure world. To avoid
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* this, clean the interrupt status register before
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* booting into the non-secure world
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*/
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tegra_memctrl_clear_pending_interrupts();
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/*
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* During boot, USB3 and flash media (SDMMC/SATA) devices need
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* access to IRAM. Because these clients connect to the MC and
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* do not have a direct path to the IRAM, the MC implements AHB
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* redirection during boot to allow path to IRAM. In this mode
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* accesses to a programmed memory address aperture are directed
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* to the AHB bus, allowing access to the IRAM. This mode must be
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* disabled before we jump to the non-secure world.
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*/
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tegra_memctrl_disable_ahb_redirection();
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/*
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* Add final timestamp before exiting BL31.
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*/
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boot_profiler_add_record("[TF] bl31 exit");
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boot_profiler_deinit();
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}
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/*******************************************************************************
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* Perform the very early platform specific architectural setup here. At the
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* moment this only intializes the mmu in a quick and dirty way.
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******************************************************************************/
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void bl31_plat_arch_setup(void)
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{
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uint64_t rw_start = BL31_RW_START;
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uint64_t rw_size = BL31_RW_END - BL31_RW_START;
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uint64_t rodata_start = BL31_RODATA_BASE;
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uint64_t rodata_size = BL31_RODATA_END - BL31_RODATA_BASE;
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uint64_t code_base = TEXT_START;
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uint64_t code_size = TEXT_END - TEXT_START;
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const mmap_region_t *plat_mmio_map = NULL;
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#if USE_COHERENT_MEM
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uint32_t coh_start, coh_size;
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#endif
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const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
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/*
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* Add timestamp for arch setup entry.
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*/
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boot_profiler_add_record("[TF] arch setup entry");
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/* add MMIO space */
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plat_mmio_map = plat_get_mmio_map();
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if (plat_mmio_map != NULL) {
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mmap_add(plat_mmio_map);
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} else {
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WARN("MMIO map not available\n");
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}
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/* add memory regions */
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mmap_add_region(rw_start, rw_start,
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rw_size,
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MT_MEMORY | MT_RW | MT_SECURE);
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mmap_add_region(rodata_start, rodata_start,
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rodata_size,
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MT_RO_DATA | MT_SECURE);
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mmap_add_region(code_base, code_base,
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code_size,
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MT_CODE | MT_SECURE);
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#if USE_COHERENT_MEM
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coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
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coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
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mmap_add_region(coh_start, coh_start,
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coh_size,
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(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE);
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#endif
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/* map TZDRAM used by BL31 as coherent memory */
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if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
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mmap_add_region(params_from_bl2->tzdram_base,
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params_from_bl2->tzdram_base,
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BL31_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE);
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}
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/* set up translation tables */
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init_xlat_tables();
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/* enable the MMU */
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enable_mmu_el3(0);
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/*
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* Add timestamp for arch setup exit.
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*/
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boot_profiler_add_record("[TF] arch setup exit");
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INFO("BL3-1: Tegra: MMU enabled\n");
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}
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/*******************************************************************************
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* Check if the given NS DRAM range is valid
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******************************************************************************/
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int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
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{
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uint64_t end = base + size_in_bytes - U(1);
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int32_t ret = 0;
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/*
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* Check if the NS DRAM address is valid
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*/
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if ((base < TEGRA_DRAM_BASE) || (base >= TEGRA_DRAM_END) ||
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(end > TEGRA_DRAM_END)) {
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ERROR("NS address 0x%llx is out-of-bounds!\n", base);
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ret = -EFAULT;
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}
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/*
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* TZDRAM aperture contains the BL31 and BL32 images, so we need
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* to check if the NS DRAM range overlaps the TZDRAM aperture.
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*/
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if ((base < (uint64_t)TZDRAM_END) && (end > tegra_bl31_phys_base)) {
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ERROR("NS address 0x%llx overlaps TZDRAM!\n", base);
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ret = -ENOTSUP;
|
|
}
|
|
|
|
/* valid NS address */
|
|
return ret;
|
|
}
|