48 lines
1.0 KiB
C
48 lines
1.0 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#define TIMER_BASE_ADDR 0x02B00000
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uint64_t ls_get_timer(uint64_t start)
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{
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return read_cntpct_el0() * 1000 / read_cntfrq_el0() - start;
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}
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static uint32_t ls_timeus_get_value(void)
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{
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/*
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* Generic delay timer implementation expects the timer to be a down
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* counter. We apply bitwise NOT operator to the tick values returned
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* by read_cntpct_el0() to simulate the down counter. The value is
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* clipped from 64 to 32 bits.
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*/
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return (uint32_t)(~read_cntpct_el0());
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}
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static const timer_ops_t ls_timer_ops = {
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.get_timer_value = ls_timeus_get_value,
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.clk_mult = 1,
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.clk_div = 25,
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};
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/*
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* Initialise the nxp layerscape on-chip free rolling us counter as the delay
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* timer.
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*/
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void ls_delay_timer_init(void)
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{
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uintptr_t cntcr = TIMER_BASE_ADDR;
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mmio_write_32(cntcr, 0x1);
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timer_init(&ls_timer_ops);
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}
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